5 Commits

Author	SHA1	Message	Date
tangxifan	0a94763422	[lib] add module rename assistant	2023-09-22 18:16:01 -07:00
tangxifan	72a3c05747	[core] code format	2023-09-17 13:29:30 -07:00
tangxifan	ccd4c1861b	[core] developing new command to write module naming rules	2023-09-16 19:37:06 -07:00
tangxifan	b5cf08a3c5	[lib] add testing	2023-09-15 17:15:05 -07:00
tangxifan	af67b02cca	[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules	2023-09-15 13:51:14 -07:00