AurelienUoU
|
bf13c1f731
|
Add a script to create a new file with correct path rather than overwrite the existing
|
2019-06-11 14:28:58 -06:00 |
|
AurelienUoU
|
345a081eff
|
Correct error of target to rewrite file in regression test
|
2019-06-07 17:37:56 -06:00 |
|
AurelienUoU
|
182d49da45
|
Update regression test scripts
|
2019-06-06 11:47:51 -06:00 |
|
AurelienUoU
|
a2f6ded2a2
|
Add path modification in file changing a keyword into OpenFPGA full path
|
2019-06-04 15:21:15 -06:00 |
|
AurelienUoU
|
17ad905b14
|
Update flow and allow netlist generation
|
2019-05-17 17:00:38 -06:00 |
|
AurelienUoU
|
f31339bb5c
|
Correctly instantiate script variables
|
2019-05-16 14:30:16 -06:00 |
|
AurelienUoU
|
c4ccff4562
|
Move Verilog test in another script to avoid false failure
|
2019-05-16 09:05:30 -06:00 |