3 Commits

Author	SHA1	Message	Date
AurelienUoU	2b04376209	Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks	2019-05-22 13:44:48 -06:00
AurelienUoU	b4c97f86a3	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
AurelienUoU	df8bb0db1a	Add MCNC Benchmarks netlists generation to travis regression test	2019-05-17 15:22:04 -06:00