4 Commits

Author	SHA1	Message	Date
tangxifan	8f5a684b10	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
tangxifan	e811f8bb21	plug in netlist manager and now the include_netlist appears in one unique file	2020-04-23 20:42:11 -06:00
tangxifan	60f40a9657	use constant module manager as much as possible in Verilog writer	2020-02-16 16:35:26 -07:00
tangxifan	99c3712b6f	adapt Verilog wire module writer	2020-02-16 12:59:37 -07:00