tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
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185e574738
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removed redundant include files in all the verilog netlists except the top one
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2020-04-24 20:21:32 -06:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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2eba882332
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |