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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3 Commits
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tangxifan
8f5a684b10
removed redundant include files in all the verilog netlists except the top one
2020-06-11 19:28:13 -06:00
tangxifan
e811f8bb21
plug in netlist manager and now the include_netlist appears in one unique file
2020-04-23 20:42:11 -06:00
tangxifan
c9d8120ae0
adapt Verilog mux writer
2020-02-16 12:35:41 -07:00