tangxifan
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7fe240e199
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[vpr] fixed a bug when parsing conventional pin loc
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2022-09-08 16:53:00 -07:00 |
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tangxifan
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765712a263
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[vpr] fixed a bug when parsing instances
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2022-09-08 16:47:28 -07:00 |
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tangxifan
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c71b533e9f
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[vpr] syntax
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2022-09-08 16:04:25 -07:00 |
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tangxifan
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b943d79092
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[vpr] now support the definition of subtile in custom pin location, such io[3:4].a2f[0:0]
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2022-09-08 15:57:08 -07:00 |
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tangxifan
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1d96974b99
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[Tool] Patch to remove compiler warnings
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2021-02-04 16:54:04 -07:00 |
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tangxifan
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2483154c34
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[Tool] Patch disable_packing XML syntax to be consistent with VPR upstream
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2021-02-04 16:28:32 -07:00 |
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tangxifan
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dd4f83a374
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bug fixing to constant string to display interconnect names
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2020-04-07 18:28:19 -06:00 |
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tangxifan
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13cd48c119
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add support on packable/unpackable modes in VPR architecture
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2020-04-06 16:07:49 -06:00 |
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tangxifan
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610c71671f
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experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
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2020-03-24 16:47:45 -06:00 |
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tangxifan
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708fda9606
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fixed a bug in using tileable routing when directlist is enabled
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2020-03-20 16:38:58 -06:00 |
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tangxifan
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a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
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5be118d695
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tileable rr_graph builder ready to debug
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2020-03-06 16:18:45 -07:00 |
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tangxifan
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5006a4395d
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bring RRGraph object and writer online
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2020-01-31 16:39:40 -07:00 |
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tangxifan
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75c3507acf
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add verbose output option for openfpga linking architecture
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2020-01-31 11:36:58 -07:00 |
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tangxifan
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8a7a4dc48e
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add physical type annotation for interconnects and inference
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2020-01-28 21:59:10 -07:00 |
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tangxifan
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5ecb771673
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debugging the annotation to physical mode of pb_types
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2020-01-27 17:43:22 -07:00 |
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tangxifan
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a6fbbce33e
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start developing the openfpga arch binding to vpr
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2020-01-27 15:31:12 -07:00 |
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tangxifan
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f1bafffa87
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add vpr8 libs and core engine for further integration
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2020-01-03 16:14:42 -07:00 |