Lin
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5174b7a336
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add capnp for unique blocks and add write bin function
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2024-09-26 17:39:52 +08:00 |
tangxifan
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af67b02cca
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[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
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2023-09-15 13:51:14 -07:00 |
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tangxifan
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3bc959dcec
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[lib] create tile config lib and start integration to core
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2023-07-14 12:13:31 -07:00 |
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tangxifan
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7961223eac
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[core] enabling io naming rules in fabric builder
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2023-06-22 22:18:09 -07:00 |
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tangxifan
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e175472a07
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[core] adding new commands
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2023-02-22 21:58:25 -08:00 |
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tangxifan
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46368de6ff
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[script] now cmake allows strict compilation
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2023-01-31 12:41:15 -08:00 |
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tangxifan
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90bbb50047
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[script] rename shared library name for tcl, so that it is straightforward to load in tcl
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2022-12-01 15:59:52 -08:00 |
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tangxifan
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338e191f77
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[script] enable swig flags when compiling vtr
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2022-12-01 15:16:58 -08:00 |
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tangxifan
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78d4991a4e
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[script] add missing flags required
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2022-12-01 14:49:05 -08:00 |
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tangxifan
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33b400de39
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[script] compilation passed but failed when loading .so to tclsh
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2022-12-01 13:51:50 -08:00 |
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tangxifan
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819b716260
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[script] debugging
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2022-12-01 12:30:57 -08:00 |
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tangxifan
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2e585024f7
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[script] debugging
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2022-12-01 12:26:30 -08:00 |
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tangxifan
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48a9a97562
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[script] enabling swig in cmake compilation
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2022-12-01 12:23:01 -08:00 |
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tangxifan
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0574efa9b3
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[script] reworking cmakefile for swig integration
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2022-12-01 12:06:27 -08:00 |
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tangxifan
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74b32c3a5c
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[script] enable shared library for openfpga
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2022-12-01 11:42:25 -08:00 |
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tangxifan
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b432ac05b4
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[script] fixed typo on IPO options
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2022-08-24 21:51:29 -07:00 |
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tangxifan
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f853040875
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[script] enable IPO in cmakefile
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2022-08-24 14:34:33 -07:00 |
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tangxifan
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800ce6a290
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[engine] avoid function naming conflicts
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2022-08-18 19:33:56 -07:00 |
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tangxifan
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a52597361b
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[script] remove duplicated libraries in dependency list for some libopenfpga
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2022-08-18 11:34:01 -07:00 |
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tangxifan
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2a5bffa6b9
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[engine] developing pcf2place integration to openfpga
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2022-07-28 10:30:43 -07:00 |
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tangxifan
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27fea8bbbe
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[lib] Merge librepackdc into libpcf
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2022-07-26 15:54:32 -07:00 |
taoli4rs
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cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
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tangxifan
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38601f325b
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[Engine] Add bus group to OpenFPGA core
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2022-02-17 17:28:55 -08:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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ad7a54db1b
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[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
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4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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675a59ecb8
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Move fpga_bitstream to the libopenfpga library and add XML reader
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2020-06-20 18:25:17 -06:00 |
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tangxifan
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3499b4d3e7
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add fabric key writer for top-level module
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2020-06-12 10:41:34 -06:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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523f9ac391
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start implement openfpga shell and use vpr as a macro
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2020-01-22 20:20:10 -07:00 |