Lin
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faa222f2c1
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create capnp folder
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2024-09-25 18:42:04 +08:00 |
tangxifan
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af67b02cca
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[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
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2023-09-15 13:51:14 -07:00 |
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tangxifan
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3bc959dcec
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[lib] create tile config lib and start integration to core
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2023-07-14 12:13:31 -07:00 |
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tangxifan
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b42677aa9d
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[lib] developing the io name mapping data structure
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2023-06-21 17:33:40 -07:00 |
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tangxifan
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b2ef1db5f4
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[lib] finishing up code changes; start debugging
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2023-02-22 20:46:18 -08:00 |
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tangxifan
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e909f4fabe
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[lib] rename libopenfpga to libs
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2022-08-18 10:27:20 -07:00 |
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tangxifan
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075900a7c9
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[engine] remove out-of-date codes due to the upgrades in VTR submodule
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2022-08-16 13:56:08 -07:00 |
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tangxifan
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48ecb6e48b
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immigrate XML parser for circuit_lib to library readarchopenfpga
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2020-01-12 18:11:00 -07:00 |
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tangxifan
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f1bafffa87
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add vpr8 libs and core engine for further integration
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2020-01-03 16:14:42 -07:00 |
Ganesh Gore
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a3e9b4aea9
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Added mINI/lib - INI Read write to project
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2019-09-27 13:58:48 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |