4 Commits

Author	SHA1	Message	Date
tangxifan	48ecb6e48b	immigrate XML parser for circuit_lib to library readarchopenfpga	2020-01-12 18:11:00 -07:00
tangxifan	f1bafffa87	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00
Ganesh Gore	a3e9b4aea9	Added mINI/lib - INI Read write to project	2019-09-27 13:58:48 -06:00
tangxifan	44d21ebb90	fixed a bug in Verilog generator supporting SRAM5T	2019-06-13 14:42:39 -06:00