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bug fixed in register scan-chain architecture

This commit is contained in:
tangxifan 2020-04-07 17:06:16 -06:00
parent 2342d7cdc6
commit ff7ea99381
1 changed files with 6 additions and 4 deletions
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10
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
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@ -439,10 +439,12 @@
<direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fle.cin" output="fabric.cin"/>
<direct name="direct3" input="fle.regin" output="fabric.regin"/>
<direct name="direct4" input="fabric.out" output="fle.out"/>
<direct name="direct5" input="fabric.cout" output="fle.cout"/>
<direct name="direct6" input="fabric.regout" output="fle.regout"/>
<direct name="direct7" input="fle.clk" output="fabric.clk"/>
<direct name="direct4" input="fle.scin" output="fabric.scin"/>
<direct name="direct5" input="fabric.out" output="fle.out"/>
<direct name="direct6" input="fabric.cout" output="fle.cout"/>
<direct name="direct7" input="fabric.regout" output="fle.regout"/>
<direct name="direct8" input="fabric.scout" output="fle.scout"/>
<direct name="direct9" input="fle.clk" output="fabric.clk"/>
</interconnect>
</mode>
<!-- Physical mode definition end (physical implementation of the fle) -->