From ff7ea9938154a939c617ad92c65d9be18c727842 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 17:06:16 -0600
Subject: [PATCH] bug fixed in register scan-chain architecture

---
 ...rac_N10_tileable_adder_register_scan_chain_40nm.xml | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index 0bce05d74..f83919c7c 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -439,10 +439,12 @@
             <direct name="direct1" input="fle.in" output="fabric.in"/>
             <direct name="direct2" input="fle.cin" output="fabric.cin"/>
             <direct name="direct3" input="fle.regin" output="fabric.regin"/>
-            <direct name="direct4" input="fabric.out" output="fle.out"/>
-            <direct name="direct5" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct6" input="fabric.regout" output="fle.regout"/>
-            <direct name="direct7" input="fle.clk" output="fabric.clk"/>
+            <direct name="direct4" input="fle.scin" output="fabric.scin"/>
+            <direct name="direct5" input="fabric.out" output="fle.out"/>
+            <direct name="direct6" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct7" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct8" input="fabric.scout" output="fle.scout"/>
+            <direct name="direct9" input="fle.clk" output="fabric.clk"/>
           </interconnect>
         </mode>
         <!-- Physical mode definition end (physical implementation of the fle) -->