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[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers

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tangxifan 2021-10-01 16:52:06 -07:00
parent 9e5debabe1
commit ff6f7e80f6
1 changed files with 2 additions and 1 deletions
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openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
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@ -8,7 +8,8 @@
<clock_setting>
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
<programming frequency="100e6">
<clock name="shift_register_clk" port="sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
<clock name="bl_shift_register_clk" port="bl_sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
<clock name="wl_shift_register_clk" port="wl_sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
</programming>
</clock_setting>
<simulator_option>