From ff6f7e80f6c19a0a4d0b9c23252b668019fc6d00 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 Oct 2021 16:52:06 -0700
Subject: [PATCH] [Flow] Modify simulation setting example for QuickLogic
 memory bank using separated clks for BL and WL shift registers

---
 .../auto_shift_register_sim_openfpga.xml                       | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
index 9b7ffa365..0f5c417ec 100644
--- a/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
+++ b/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
@@ -8,7 +8,8 @@
   <clock_setting>
     <operating frequency="auto" num_cycles="auto" slack="0.2"/>
     <programming frequency="100e6">
-      <clock name="shift_register_clk" port="sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
+      <clock name="bl_shift_register_clk" port="bl_sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
+      <clock name="wl_shift_register_clk" port="wl_sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
     </programming>
   </clock_setting>
   <simulator_option>