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[core] debug

This commit is contained in:
tangxifan 2024-07-05 11:17:05 -07:00
parent f6adca1545
commit fdbc427f70
2 changed files with 5 additions and 5 deletions
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8
openfpga/src/annotation/annotate_rr_graph.cpp
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@ -115,13 +115,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
std::map<e_side, vtr::Point<size_t>> track_range; std::map<e_side, vtr::Point<size_t>> track_range;
track_range[TOP] = vtr::Point<size_t>(0, gsb_range.y()); track_range[TOP] = vtr::Point<size_t>(0, gsb_range.y());
track_range[RIGHT] = vtr::Point<size_t>(0, gsb_range.x()); track_range[RIGHT] = vtr::Point<size_t>(0, gsb_range.x());
track_range[BOTTOM] = vtr::Point<size_t>(1, gsb_range.y()); track_range[BOTTOM] = vtr::Point<size_t>(0, gsb_range.y());
track_range[LEFT] = vtr::Point<size_t>(1, gsb_range.x()); track_range[LEFT] = vtr::Point<size_t>(0, gsb_range.x());
if (perimeter_cb) { if (perimeter_cb) {
track_range[TOP] = vtr::Point<size_t>(0, gsb_range.y() + 1); track_range[TOP] = vtr::Point<size_t>(0, gsb_range.y() + 1);
track_range[RIGHT] = vtr::Point<size_t>(0, gsb_range.x() + 1); track_range[RIGHT] = vtr::Point<size_t>(0, gsb_range.x() + 1);
track_range[BOTTOM] = vtr::Point<size_t>(0, gsb_range.y() + 2); track_range[BOTTOM] = vtr::Point<size_t>(0, gsb_range.y() + 1);
track_range[LEFT] = vtr::Point<size_t>(0, gsb_range.x() + 2); track_range[LEFT] = vtr::Point<size_t>(0, gsb_range.x() + 1);
} }
/* Create an object to return */ /* Create an object to return */

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit b06f2ee34036a8c981a2c202ec06251c1bb2b81a Subproject commit de0d0bc214419cae53c10e6a1349d4ae251625f8