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[Doc] Update documentation about the pre-processing flags

This commit is contained in:
tangxifan 2020-11-22 20:33:15 -07:00
parent 3b2a4c5387
commit fd0e6814ea
2 changed files with 14 additions and 12 deletions
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12
docs/source/manual/fpga_verilog/fabric_netlist.rst
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@ -48,18 +48,6 @@ Top-level Netlists
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
Logic Blocks Logic Blocks
~~~~~~~~~~~~ ~~~~~~~~~~~~
This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks. This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks.

14
docs/source/manual/fpga_verilog/testbench.rst
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@ -80,6 +80,20 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: <bench_name>_autocheck_top_tb.v .. option:: <bench_name>_autocheck_top_tb.v
This is the netlist for full testbench. This is the netlist for full testbench.