From fd0e6814eab68183d2b09a569cc7f39774172d5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 20:33:15 -0700 Subject: [PATCH] [Doc] Update documentation about the pre-processing flags --- docs/source/manual/fpga_verilog/fabric_netlist.rst | 12 ------------ docs/source/manual/fpga_verilog/testbench.rst | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/docs/source/manual/fpga_verilog/fabric_netlist.rst b/docs/source/manual/fpga_verilog/fabric_netlist.rst index 46c8a934b..f09575a84 100644 --- a/docs/source/manual/fpga_verilog/fabric_netlist.rst +++ b/docs/source/manual/fpga_verilog/fabric_netlist.rst @@ -48,18 +48,6 @@ Top-level Netlists .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command. - - .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - - - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command. - - .. warning:: Please disable this flag if you are not using icarus iVerilog simulator. - -__ iverilog_website_ - -.. _iverilog_website: http://iverilog.icarus.com/ - Logic Blocks ~~~~~~~~~~~~ This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks. diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index db3ed8835..d6cd518fe 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -80,6 +80,20 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! + - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command. + + .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. + + - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command. + + .. warning:: Please disable this flag if you are not using icarus iVerilog simulator. + +__ iverilog_website_ + +.. _iverilog_website: http://iverilog.icarus.com/ + + + .. option:: _autocheck_top_tb.v This is the netlist for full testbench.