riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Verilog] Fixed a bug in naming mismatch

This commit is contained in:
tangxifan 2022-02-13 20:06:35 -08:00
parent a068237082
commit fb4106de19
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -153,8 +153,8 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
/* Always use explicit port mapping */
print_verilog_testbench_benchmark_instance(fp, std::string(circuit_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)),
std::string(FPGA_INSTANCE_NAME),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(),
std::string(),
std::vector<std::string>(),
std::string(FPGA_PORT_POSTFIX),
atom_ctx, netlist_annotation,

4
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -54,7 +54,9 @@ void print_verilog_testbench_fpga_instance(std::fstream& fp,
if (!net_postfix.empty()) {
for (const ModulePortId &module_port_id : module_manager.module_ports(top_module)) {
BasicPort module_port = module_manager.module_port(top_module, module_port_id);
port2port_name_map[module_port.get_name()] = module_port.get_name() + net_postfix;
BasicPort net_port = module_port;
net_port.set_name(module_port.get_name() + net_postfix);
port2port_name_map[module_port.get_name()] = net_port;
}
}