From fb4106de190e40c4be962a89f2f026223dd9cc3c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 13 Feb 2022 20:06:35 -0800
Subject: [PATCH] [FPGA-Verilog] Fixed a bug in naming mismatch

---
 .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp  | 4 ++--
 openfpga/src/fpga_verilog/verilog_testbench_utils.cpp         | 4 +++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index a4b24e769..1a9aa605a 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -153,8 +153,8 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
   /* Always use explicit port mapping */
   print_verilog_testbench_benchmark_instance(fp, std::string(circuit_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)),
                                              std::string(FPGA_INSTANCE_NAME),
-                                             std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
-                                             std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
+                                             std::string(),
+                                             std::string(),
                                              std::vector<std::string>(),
                                              std::string(FPGA_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index 4e16ab6e7..1e54ca9d5 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -54,7 +54,9 @@ void print_verilog_testbench_fpga_instance(std::fstream& fp,
   if (!net_postfix.empty()) { 
     for (const ModulePortId &module_port_id : module_manager.module_ports(top_module)) {
       BasicPort module_port = module_manager.module_port(top_module, module_port_id);
-      port2port_name_map[module_port.get_name()] = module_port.get_name() + net_postfix;
+      BasicPort net_port = module_port;
+      net_port.set_name(module_port.get_name() + net_postfix);
+      port2port_name_map[module_port.get_name()] = net_port;
     }
   }