added signal gen regression test to shell script
This commit is contained in:
Andrew Pond
parent
477cba1c7e
commit
fab2b069f0
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@ -38,35 +38,26 @@ module bitstream_loader(
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wire bram_output;
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assign config_chain_head = bram_output;
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RAMB18E1 #(
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// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
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.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
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// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
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.SIM_COLLISION_CHECK("ALL"),
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// RAM Mode: "SDP" or "TDP"
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.RAM_MODE("TDP"),
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// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
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.READ_WIDTH_A(1), // 0-72
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.READ_WIDTH_B(0), // 0-18
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.WRITE_WIDTH_A(0), // 0-18
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.WRITE_WIDTH_B(0), // 0-72
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EFX_RAM_5K #(
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.READ_WIDTH(1),
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.WRITE_WIDTH(0),
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.INIT_00(256'h00000000000000000000000000000000000000000000007f00000000000000ff),
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.INIT_01(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000),
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.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_04(256'h00000003f8000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000078000000000000000000000000000000000000000000000),
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.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff),
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.INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000),
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.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000),
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.INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000),
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.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
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@ -75,92 +66,20 @@ module bitstream_loader(
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.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000),
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.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
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.RSTREG_PRIORITY_A("RSTREG"),
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.RSTREG_PRIORITY_B("RSTREG"),
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// SRVAL_A, SRVAL_B: Set/reset value for output
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.SRVAL_A(18'hFFFFF),
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.SRVAL_B(18'h00000),
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// Simulation Device: Must be set to "7SERIES" for simulation behavior
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.SIM_DEVICE("7SERIES"),
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// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST")
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)
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RAMB18E1_inst (
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EFX_RAM_5K_inst (
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// Port A Data: 16-bit (each) output: Port A data
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.DOADO(bram_output), // 16-bit output: A port data/LSB data
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.DOPADOP(), // 2-bit output: A port parity/LSB parity
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// Port B Data: 16-bit (each) output: Port B data
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.DOBDO(), // 16-bit output: B port data/MSB data
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.DOPBDOP(), // 2-bit output: B port parity/MSB parity
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// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
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// when RAM_MODE="SDP")
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.ADDRARDADDR(bram_addr), // 14-bit input: A port address/Read address
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.CLKARDCLK(~prog_clk), // 1-bit input: A port clock/Read clock
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.ENARDEN(1'b1), // 1-bit input: A port enable/Read enable
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.REGCEAREGCE(1'b1), // 1-bit input: A port register enable/Register enable
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.RSTRAMARSTRAM(0), // 1-bit input: A port set/reset
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.RSTREGARSTREG(0), // 1-bit input: A port register set/reset
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.WEA(2'b00), // 2-bit input: A port write enable
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// Port A Data: 16-bit (each) input: Port A data
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.DIADI(0), // 16-bit input: A port data/LSB data
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.DIPADIP(0), // 2-bit input: A port parity/LSB parity
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// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
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// when RAM_MODE="SDP")
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.ADDRBWRADDR(0), // 14-bit input: B port address/Write address
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.CLKBWRCLK(0), // 1-bit input: B port clock/Write clock
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.ENBWREN(0), // 1-bit input: B port enable/Write enable
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.REGCEB(0), // 1-bit input: B port register enable
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.RSTRAMB(0), // 1-bit input: B port set/reset
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.RSTREGB(0), // 1-bit input: B port register set/reset
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.WEBWE(0), // 4-bit input: B port write enable/Write enable
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// Port B Data: 16-bit (each) input: Port B data
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.DIBDI(0), // 16-bit input: B port data/MSB data
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.DIPBDIP(0) // 2-bit input: B port parity/MSB parity
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.WDATA(0), // Write data
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.WADDR(0), // Write address
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.WE(0), // Write enable
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.WCLK(0),
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.WCLKE(0),
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.RDATA(bram_output),
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.RADDR(bram_addr),
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.RE(1'b1),
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.RCLK(prog_clk)
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);
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@ -15,3 +15,6 @@ run-task benchmark_sweep/mac_units --debug --show_thread_logs
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# Otherwise, it will fail
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run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
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#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
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run-task benchmark_sweep/signal_gen --debug --show_thread_logs
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