From fab2b069f0bb83dc27530c70e8f79fd2612024e9 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Wed, 30 Jun 2021 16:18:09 -0600 Subject: [PATCH] added signal gen regression test to shell script --- .../config_loader/bitstream_loader.v | 143 ++++-------------- .../micro_benchmark_reg_test.sh | 3 + 2 files changed, 34 insertions(+), 112 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v index 68b04aee1..69a92ff92 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v +++ b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v @@ -38,35 +38,26 @@ module bitstream_loader( wire bram_output; assign config_chain_head = bram_output; - RAMB18E1 #( - // Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE" - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - // Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") - .SIM_COLLISION_CHECK("ALL"), - // RAM Mode: "SDP" or "TDP" - .RAM_MODE("TDP"), - // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port - .READ_WIDTH_A(1), // 0-72 - .READ_WIDTH_B(0), // 0-18 - .WRITE_WIDTH_A(0), // 0-18 - .WRITE_WIDTH_B(0), // 0-72 + EFX_RAM_5K #( + .READ_WIDTH(1), + .WRITE_WIDTH(0), - .INIT_00(256'h00000000000000000000000000000000000000000000007f00000000000000ff), - .INIT_01(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), - .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_04(256'h00000003f8000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000078000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff), + .INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), + .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000), + .INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000), + .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), @@ -75,92 +66,20 @@ module bitstream_loader( .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - - - - // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE") - .RSTREG_PRIORITY_A("RSTREG"), - .RSTREG_PRIORITY_B("RSTREG"), - // SRVAL_A, SRVAL_B: Set/reset value for output - .SRVAL_A(18'hFFFFF), - .SRVAL_B(18'h00000), - // Simulation Device: Must be set to "7SERIES" for simulation behavior - .SIM_DEVICE("7SERIES"), - // WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE") - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST") ) - RAMB18E1_inst ( + EFX_RAM_5K_inst ( // Port A Data: 16-bit (each) output: Port A data - .DOADO(bram_output), // 16-bit output: A port data/LSB data - .DOPADOP(), // 2-bit output: A port parity/LSB parity - // Port B Data: 16-bit (each) output: Port B data - .DOBDO(), // 16-bit output: B port data/MSB data - .DOPBDOP(), // 2-bit output: B port parity/MSB parity - // Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port - // when RAM_MODE="SDP") - .ADDRARDADDR(bram_addr), // 14-bit input: A port address/Read address - .CLKARDCLK(~prog_clk), // 1-bit input: A port clock/Read clock - .ENARDEN(1'b1), // 1-bit input: A port enable/Read enable - .REGCEAREGCE(1'b1), // 1-bit input: A port register enable/Register enable - .RSTRAMARSTRAM(0), // 1-bit input: A port set/reset - .RSTREGARSTREG(0), // 1-bit input: A port register set/reset - .WEA(2'b00), // 2-bit input: A port write enable - // Port A Data: 16-bit (each) input: Port A data - .DIADI(0), // 16-bit input: A port data/LSB data - .DIPADIP(0), // 2-bit input: A port parity/LSB parity - // Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port - // when RAM_MODE="SDP") - .ADDRBWRADDR(0), // 14-bit input: B port address/Write address - .CLKBWRCLK(0), // 1-bit input: B port clock/Write clock - .ENBWREN(0), // 1-bit input: B port enable/Write enable - .REGCEB(0), // 1-bit input: B port register enable - .RSTRAMB(0), // 1-bit input: B port set/reset - .RSTREGB(0), // 1-bit input: B port register set/reset - .WEBWE(0), // 4-bit input: B port write enable/Write enable - // Port B Data: 16-bit (each) input: Port B data - .DIBDI(0), // 16-bit input: B port data/MSB data - .DIPBDIP(0) // 2-bit input: B port parity/MSB parity + .WDATA(0), // Write data + .WADDR(0), // Write address + .WE(0), // Write enable + + .WCLK(0), + .WCLKE(0), + + .RDATA(bram_output), + .RADDR(bram_addr), + .RE(1'b1), + .RCLK(prog_clk) ); diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 28b24aef3..0790421bb 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -15,3 +15,6 @@ run-task benchmark_sweep/mac_units --debug --show_thread_logs # Otherwise, it will fail run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim + + +run-task benchmark_sweep/signal_gen --debug --show_thread_logs