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[script] fixed a bug on wrong path to the ace2 executable

This commit is contained in:
tangxifan 2022-08-23 10:53:44 -07:00
parent ba0ddd01d3
commit fa790d50d4
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/misc/fpgaflow_default_tool_path.conf
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@ -8,7 +8,7 @@ abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
ace_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/ace2/ace ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace
pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
iverilog_path = iverilog iverilog_path = iverilog
include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists