From fa790d50d461acb344997f4907de17cede190468 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 10:53:44 -0700 Subject: [PATCH] [script] fixed a bug on wrong path to the ace2 executable --- openfpga_flow/misc/fpgaflow_default_tool_path.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 7c3e49803..9d0c07982 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -8,7 +8,7 @@ abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr -ace_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/ace2/ace +ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl iverilog_path = iverilog include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists