[Engine] Bug fix
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@ -1555,7 +1555,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
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for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
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for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
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for (const FabricWordLineBankId& sr_bank : sr_banks.wl_banks(config_region)) {
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for (const FabricWordLineBankId& sr_bank : sr_banks.wl_banks(config_region)) {
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size_t wl_bank_size = sr_banks.wl_bank_size(config_region, sr_bank);
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size_t wl_bank_size = sr_banks.wl_bank_size(config_region, sr_bank);
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std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), wl_bank_size);
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std::string sr_module_name = generate_wl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), wl_bank_size);
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ModuleId sr_bank_module = module_manager.find_module(sr_module_name);
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ModuleId sr_bank_module = module_manager.find_module(sr_module_name);
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VTR_ASSERT(sr_bank_module);
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VTR_ASSERT(sr_bank_module);
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@ -436,6 +436,7 @@ bool MemoryBankShiftRegisterBanks::empty() const {
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void MemoryBankShiftRegisterBanks::build_bl_port_fast_lookup() const {
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void MemoryBankShiftRegisterBanks::build_bl_port_fast_lookup() const {
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bl_ports_to_sr_bank_ids_.resize(bl_bank_data_ports_.size());
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bl_ports_to_sr_bank_ids_.resize(bl_bank_data_ports_.size());
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bl_ports_to_sr_bank_ports_.resize(bl_bank_data_ports_.size());
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for (const auto& region : bl_bank_data_ports_) {
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for (const auto& region : bl_bank_data_ports_) {
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size_t bl_index = 0;
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size_t bl_index = 0;
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for (const auto& bank : region) {
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for (const auto& bank : region) {
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@ -458,6 +459,7 @@ void MemoryBankShiftRegisterBanks::build_bl_port_fast_lookup() const {
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void MemoryBankShiftRegisterBanks::build_wl_port_fast_lookup() const {
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void MemoryBankShiftRegisterBanks::build_wl_port_fast_lookup() const {
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wl_ports_to_sr_bank_ids_.resize(wl_bank_data_ports_.size());
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wl_ports_to_sr_bank_ids_.resize(wl_bank_data_ports_.size());
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wl_ports_to_sr_bank_ports_.resize(wl_bank_data_ports_.size());
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for (const auto& region : wl_bank_data_ports_) {
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for (const auto& region : wl_bank_data_ports_) {
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size_t wl_index = 0;
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size_t wl_index = 0;
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for (const auto& bank : region) {
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for (const auto& bank : region) {
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