diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp index 900eb8bb3..88062d5b2 100644 --- a/openfpga/src/fabric/build_top_module_memory_bank.cpp +++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp @@ -1555,7 +1555,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { for (const FabricWordLineBankId& sr_bank : sr_banks.wl_banks(config_region)) { size_t wl_bank_size = sr_banks.wl_bank_size(config_region, sr_bank); - std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), wl_bank_size); + std::string sr_module_name = generate_wl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), wl_bank_size); ModuleId sr_bank_module = module_manager.find_module(sr_module_name); VTR_ASSERT(sr_bank_module); diff --git a/openfpga/src/fabric/memory_bank_shift_register_banks.cpp b/openfpga/src/fabric/memory_bank_shift_register_banks.cpp index 048655533..a593f2831 100644 --- a/openfpga/src/fabric/memory_bank_shift_register_banks.cpp +++ b/openfpga/src/fabric/memory_bank_shift_register_banks.cpp @@ -436,6 +436,7 @@ bool MemoryBankShiftRegisterBanks::empty() const { void MemoryBankShiftRegisterBanks::build_bl_port_fast_lookup() const { bl_ports_to_sr_bank_ids_.resize(bl_bank_data_ports_.size()); + bl_ports_to_sr_bank_ports_.resize(bl_bank_data_ports_.size()); for (const auto& region : bl_bank_data_ports_) { size_t bl_index = 0; for (const auto& bank : region) { @@ -458,6 +459,7 @@ void MemoryBankShiftRegisterBanks::build_bl_port_fast_lookup() const { void MemoryBankShiftRegisterBanks::build_wl_port_fast_lookup() const { wl_ports_to_sr_bank_ids_.resize(wl_bank_data_ports_.size()); + wl_ports_to_sr_bank_ports_.resize(wl_bank_data_ports_.size()); for (const auto& region : wl_bank_data_ports_) { size_t wl_index = 0; for (const auto& bank : region) {