minor tuning on ini compilation
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@ -8,5 +8,6 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
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#Create the library
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add_library(libini STATIC
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${LIB_HEADERS})
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target_include_directories(libini PUBLIC ${LIB_INCLUDE_DIRS})
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set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX)
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@ -22,13 +22,13 @@
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* Top-level function to write an ini file which contains exchangeable
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* information, in order to interface different Verilog simulators
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********************************************************************/
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void print_verilog_simulation_info(const int &num_operating_clock_cycles,
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const std::string &verilog_dir_formatted,
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const std::string &chomped_circuit_name,
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const std::string &src_dir_path,
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const size_t &num_program_clock_cycles,
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const float &prog_clock_freq,
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const float &op_clock_freq) {
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void print_verilog_simulation_info(const int& num_operating_clock_cycles,
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const std::string& verilog_dir_formatted,
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const std::string& chomped_circuit_name,
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const std::string& src_dir_path,
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const size_t& num_program_clock_cycles,
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const float& prog_clock_freq,
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const float& op_clock_freq) {
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mINI::INIStructure ini;
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// std::map<char, int> units_map;
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// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
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@ -3,11 +3,11 @@
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#include <string>
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void print_verilog_simulation_info(const int &num_operating_clock_cycles,
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const std::string &verilog_dir_formatted,
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const std::string &chomped_circuit_name,
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const std::string &src_dir_path,
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const size_t &num_program_clock_cycles,
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const float &prog_clock_freq,
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const float &op_clock_freq);
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void print_verilog_simulation_info(const int& num_operating_clock_cycles,
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const std::string& verilog_dir_formatted,
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const std::string& chomped_circuit_name,
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const std::string& src_dir_path,
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const size_t& num_program_clock_cycles,
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const float& prog_clock_freq,
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const float& op_clock_freq);
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#endif
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