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update ducoumentation to explain lib_name XML syntax

This commit is contained in:
tangxifan 2020-01-08 14:22:17 -07:00
parent 4877cfd36a
commit f67981afa8
1 changed files with 4 additions and 2 deletions
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6
docs/source/arch_lang/circuit_modules.rst
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@ -54,7 +54,7 @@ Transistor level
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<pass_gate_logic type="string" circuit_model_name="string"/>
<port type="string" prefix="string" size="int" default_val="int" circuit_model_name="string"
<port type="string" prefix="string" lib_name="string" size="int" default_val="int" circuit_model_name="string"
mode_select="boolean" is_global="boolean" is_set="boolean" is_reset="boolean"
is_config_enable="boolean"/>
</circuit_model>
@ -79,7 +79,9 @@ Transistor level
* **type:** can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
* **prefix:** the name of the port. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
* **prefix:** the name of the port to appear in the autogenerated netlists. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
* **lib_name:** the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``.
* **size:** bandwidth of the port.