From f67981afa8db83a36476a4ca2fcda2e8bda0d6eb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 8 Jan 2020 14:22:17 -0700 Subject: [PATCH] update ducoumentation to explain lib_name XML syntax --- docs/source/arch_lang/circuit_modules.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/source/arch_lang/circuit_modules.rst b/docs/source/arch_lang/circuit_modules.rst index 96cc38f13..e7f4e736a 100644 --- a/docs/source/arch_lang/circuit_modules.rst +++ b/docs/source/arch_lang/circuit_modules.rst @@ -54,7 +54,7 @@ Transistor level - @@ -79,7 +79,9 @@ Transistor level * **type:** can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined. - * **prefix:** the name of the port. Each port will be shown as ``[i]`` in Verilog/SPICE netlists. + * **prefix:** the name of the port to appear in the autogenerated netlists. Each port will be shown as ``[i]`` in Verilog/SPICE netlists. + + * **lib_name:** the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``. * **size:** bandwidth of the port.