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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev

This commit is contained in:
ganeshgore 2020-07-27 16:23:43 -06:00
parent 45af056304 cec6bf0b6f
commit f6196f6a3b
144 changed files with 14013 additions and 496 deletions
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5
.travis/basic_reg_test.sh
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@ -36,7 +36,7 @@ echo -e "Testing Verilog testbench generation only";
python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs
echo -e "Testing bitstream generation only";
python3 openfpga_flow/scripts/run_fpga_task.py generate_bitstream --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs
@ -44,4 +44,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug
echo -e "Testing SDC generation with time units";
python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs
echo -e "Testing FPGA-SPICE with netlist generation";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
end_section "OpenFPGA.TaskTun"

6
.travis/verilog_reg_test.sh
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@ -75,6 +75,12 @@ python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_vanilla_key -
python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_random_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/load_external_key --debug --show_thread_logs
echo -e "Testing Power-gating designs";
python3 openfpga_flow/scripts/run_fpga_task.py power_gated_design/power_gated_inverter --show_thread_logs --debug
echo -e "Testing Depopulated crossbar in local routing";
python3 openfpga_flow/scripts/run_fpga_task.py depopulate_crossbar --debug --show_thread_logs
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail

14
docs/source/manual/arch_lang/technology_library.rst
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@ -13,8 +13,8 @@ General organization is as follows.
<device_model name="<string>" type="<string>">
<lib type="<string>" corner="<string>" ref="<string>" path="<string>"/>
<design vdd="<float>" pn_ratio="<float>"/>
<pmos name="<string>" chan_length="<float>" min_width="<float>" variation="<string>"/>
<nmos name="<string>" chan_length="<float>" min_width="<float>" variation="<string>"/>
<pmos name="<string>" chan_length="<float>" min_width="<float>" max_width="<float>" variation="<string>"/>
<nmos name="<string>" chan_length="<float>" min_width="<float>" max_width="<float>" variation="<string>"/>
<rram rlrs="<float>" rhrs="<float>" variation="<string>"/>
</device_model>
</device_library>
@ -71,15 +71,19 @@ A device model represents a transistor/RRAM model available in users' technology
- ``pn_ratio="<float>"`` specify the ratio between *p*-type and *n*-type transistors. The ratio will be used when building circuit structures such as inverters, buffers, etc.
.. option:: <pmos|nmos name="<string>" chan_length="<float>" min_width="<float>" variation="<string>"/>
.. option:: <pmos|nmos name="<string>" chan_length="<float>" min_width="<float>" max_width="<float>" variation="<string>"/>
Specify device-level parameters for transistors
- ``name="<string>"`` specify the name of the p/n type transistor, which can be found in the manual of the technology provider.
- ``chan_length="<float>"`` specify the channel length of *p/n* type transistor.
- ``chan_length="<float>"`` specify the channel length of a *p/n* type transistor.
- ``min_width="<float>"`` specify the minimum width of *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing.
- ``min_width="<float>"`` specify the minimum width of a *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing.
- ``max_width="<float>"`` specify the maximum width of a *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing. If the required transistor width exceeds the maximum width, multiple transistors will be instanciated. Note that for FinFET technology, your ``max_width`` should be the same as your ``min_width``.
.. note:: The ``max_width`` is optional. By default, it will be set to be same as the ``min_width``.
- ``variation="<string>"`` specify the variation name defined in the ``<variation_library>``

128
docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
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@ -1,7 +1,133 @@
Fabric-dependent Bitstream
~~~~~~~~~~~~~~~~~~~~~~~~~~
Usage
`````
Fabric-dependent bitstream is design to be loadable to the configuration protocols of FPGAs.
The bitstream just sets an order to the configuration bits in the database, without duplicating the database.
OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists.
The fabric-dependent bitstream can be found in autogenerated Verilog testbenches.
The fabric-dependent bitstream can be found in the pre-configured Verilog testbenches.
The fabric bitsteam can be outputted in different file format in terms of usage.
Plain Text File Format
```````````````````````
This file format is designed to be directly loaded to an FPGA fabric.
It does not include any comments but only bitstream.
The information depends on the type of configuration procotol.
.. option:: vanilla
A line consisting of ``0`` | ``1``
.. option:: scan_chain
A line consisting of ``0`` | ``1``
.. option:: memory_bank
Multiple lines will be included, each of which is organized as <address><space><bit>.
Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired.
The first line represents the Bit-Line address and configuration bit.
The second line represents the Word-Line address and configuration bit.
For example
.. code-block:: xml
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address> <bit_value>
<wordline_address> <bit_value>
...
<bitline_address> <bit_value>
<wordline_address> <bit_value>
.. option:: frame_based
Multiple lines will be included, each of which is organized as <address><space><bit>.
For example
.. code-block:: xml
<frame_address> <bit_value>
<frame_address> <bit_value>
...
<frame_address> <bit_value>
XML File Format
```````````````
This file format is designed to generate testbenches using external tools, e.g., CocoTB.
In principle, the file consist a number of XML node ``<bit>``, each bit contains the following attributes:
- ``id``: The unique id of the configuration bit in the fabric bitstream.
- ``value``: The configuration bit value.
- ``hierarchy`` represents the location of this block in FPGA fabric.
The hierachy includes the full hierarchy of this block
- ``instance`` denotes the instance name which you can find in the fabric netlists
- ``level`` denotes the depth of the block in the hierarchy
- ``width`` denotes the number of configuration bits under the instance. Typically, only leaf instance has this attribute.
A quick example:
.. code-block:: xml
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
<instance level="2" name="logical_tile_clb_mode_clb__0"/>
<instance level="3" width="10" name="mem_fle_9_in_5"/>
</hierarchy>
</bit>
Other information may depend on the type of configuration procotol.
.. option:: memory_bank
- ``bl``: Bit line address information
- ``wl``: Word line address information
A quick example:
.. code-block:: xml
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" width="1" name="iopad_sram_blwl_mem"/>
</hierarchy>
<bl address="000000"/>
<wl address="000000"/>
</bit>
.. option:: frame_based
- ``frame``: frame address information
A quick example:
.. code-block:: xml
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" width="1" name="iopad_config_latch_mem"/>
</hierarchy>
<frame address="0000000000000000"/>
</bit>

13
docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
View File

@ -7,8 +7,8 @@ repack
~~~~~~
Repack the netlist to physical pbs
This must be done before bitstream generator and testbench generation
Strongly recommend it is done after all the fix-up have been applied
.. note:: This must be done before bitstream generator and testbench generation. Strongly recommend it is done after all the fix-up have been applied
- ``--verbose`` Show verbose log
@ -28,6 +28,15 @@ build_fabric_bitstream
Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric
- ``--verbose`` Show verbose log
write_fabric_bitstream
~~~~~~~~~~~~~~~~~~~~~~
Output the fabric bitstream database to a specific file format
- ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1)
- ``--format`` Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
- ``--verbose`` Show verbose log

2
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
View File

@ -31,7 +31,7 @@ write_verilog_testbench
- ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
- ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
- ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
- ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA

4
docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
View File

@ -109,6 +109,10 @@ build_fabric
- ``--write_fabric_key <xml_file>`` Output current fabric key to an XML file
- ``--frame_view`` Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
.. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
- ``--verbose`` Show verbose log
.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE

95
libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
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@ -302,7 +302,9 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
return num_err;
}
/* Check all the ports make sure, they satisfy the restriction */
/************************************************************************
* Check all the ports make sure, they satisfy the restriction
***********************************************************************/
static
size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
size_t num_err = 0;
@ -435,6 +437,94 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
return num_err;
}
/************************************************************************
* Check the port requirements for a power-gated circuit model
* - It must have at least 2 global ports and which are config enable signals
* - It must have an Enable port which control power gating
* - It must have an EnableB port which control power gating
***********************************************************************/
static
int check_power_gated_circuit_model(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
int num_err = 0;
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
/* If the circuit model is power-gated, we need to find at least one global config_enable signals */
VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
/* Check all the ports we have are good for a power-gated circuit model */
/* We need at least one global port */
if (2 > global_ports.size()) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Expect at least two global ports (a pair of EN/Enb) for circuit model '%s' which is power-gated!\n",
circuit_lib.model_name(circuit_model).c_str());
num_err++;
}
/* All the global ports should be config_enable */
int num_config_enable_ports = 0;
for (const auto& port : global_ports) {
if (true == circuit_lib.port_is_config_enable(port)) {
num_config_enable_ports++;
}
}
if (2 != num_config_enable_ports) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Circuit model '%s' is power-gated. Two config-enable global ports are required!\n",
circuit_lib.model_name(circuit_model).c_str());
num_err++;
}
/* Report errors if there are any */
if (0 < num_err) {
return num_err;
}
/* Try to find a pair of Enable and ENb ports from the global ports */
CircuitPortId en_port = CircuitPortId::INVALID();
CircuitPortId enb_port = CircuitPortId::INVALID();
for (const auto& port : global_ports) {
/* Focus on config_enable ports which are power-gate control signals */
if (false == circuit_lib.port_is_config_enable(port)) {
continue;
}
if (0 == circuit_lib.port_default_value(port)) {
en_port = port;
} else {
VTR_ASSERT(1 == circuit_lib.port_default_value(port));
enb_port = port;
}
}
/* We must have valid EN/ENb ports */
if (false == circuit_lib.valid_circuit_port_id(en_port)) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Fail to find an enable port for the circuit model '%s' is power-gated!\n",
circuit_lib.model_name(circuit_model).c_str());
}
if (false == circuit_lib.valid_circuit_port_id(enb_port)) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Fail to find an inverted enable port for the circuit model '%s' is power-gated!\n",
circuit_lib.model_name(circuit_model).c_str());
}
return num_err;
}
/************************************************************************
* Check the port requirements for each power-gated circuit model
***********************************************************************/
static
int check_power_gated_circuit_models(const CircuitLibrary& circuit_lib) {
int num_err = 0;
for (const CircuitModelId& circuit_model : circuit_lib.models()) {
if (true == circuit_lib.is_power_gated(circuit_model)) {
num_err += check_power_gated_circuit_model(circuit_lib, circuit_model);
}
}
return num_err;
}
/************************************************************************
* Check points to make sure we have a valid circuit library
* Detailed checkpoints:
@ -541,6 +631,9 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_CHAN_WIRE);
num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_WIRE);
/* 11. Check power-gated inverter/buffer models */
num_err += check_power_gated_circuit_models(circuit_lib);
/* If we have any errors, exit */
if (0 < num_err) {

8
libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp
View File

@ -122,6 +122,14 @@ void read_xml_device_transistor(pugi::xml_node& xml_device_transistor,
tech_lib.set_transistor_model_min_width(device_model, transistor_type,
get_attribute(xml_device_transistor, "min_width", loc_data).as_float(0.));
/* Parse the transistor maximum width, by default we consider the same as minimum width */
tech_lib.set_transistor_model_max_width(device_model, transistor_type,
get_attribute(xml_device_transistor, "max_width", loc_data, pugiutil::ReqOpt::OPTIONAL).as_float(0.));
/* If the max_width is default value, we set it to be the same as min_width */
if (0. == tech_lib.transistor_model_max_width(device_model, transistor_type)) {
tech_lib.set_transistor_model_max_width(device_model, transistor_type, tech_lib.transistor_model_min_width(device_model, transistor_type));
}
/* Parse the transistor variation name */
tech_lib.set_transistor_model_variation_name(device_model, transistor_type,
get_attribute(xml_device_transistor, "variation", loc_data).as_string());

26
libopenfpga/libarchopenfpga/src/technology_library.cpp
View File

@ -157,6 +157,18 @@ float TechnologyLibrary::transistor_model_min_width(const TechnologyModelId& mod
return transistor_model_min_widths_[model_id][transistor_type];
}
/* Access the maximum width of a transistor (either PMOS or NMOS) for a technology model
* Note: This is ONLY applicable to transistor model
*/
float TechnologyLibrary::transistor_model_max_width(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* This is only applicable to transistor model */
VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == model_type(model_id));
return transistor_model_max_widths_[model_id][transistor_type];
}
/* Access the minimum width of a transistor (either PMOS or NMOS) for a technology model
* Note: This is ONLY applicable to transistor model
*/
@ -270,6 +282,7 @@ TechnologyModelId TechnologyLibrary::add_model(const std::string& name) {
transistor_model_names_.emplace_back();
transistor_model_chan_lengths_.emplace_back();
transistor_model_min_widths_.emplace_back();
transistor_model_max_widths_.emplace_back();
transistor_model_variation_names_.emplace_back();
transistor_model_variation_ids_.push_back(std::array<TechnologyVariationId, 2>{TechnologyVariationId::INVALID(), TechnologyVariationId::INVALID()});
@ -394,6 +407,19 @@ void TechnologyLibrary::set_transistor_model_min_width(const TechnologyModelId&
return;
}
/* Set the maximum width for either PMOS or NMOS of a model in the library
* This is ONLY applicable to transistors
*/
void TechnologyLibrary::set_transistor_model_max_width(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type,
const float& max_width) {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == model_type(model_id));
transistor_model_max_widths_[model_id][transistor_type] = max_width;
return;
}
/* Set the variation name for either PMOS or NMOS of a model in the library
* This is ONLY applicable to transistors
*/

14
libopenfpga/libarchopenfpga/src/technology_library.h
View File

@ -101,6 +101,8 @@ class TechnologyLibrary {
const e_tech_lib_transistor_type& transistor_type) const;
float transistor_model_min_width(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type) const;
float transistor_model_max_width(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type) const;
TechnologyVariationId transistor_model_variation(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type) const;
public: /* Public Accessors: Basic data query on RRAM models */
@ -138,6 +140,9 @@ class TechnologyLibrary {
void set_transistor_model_min_width(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type,
const float& min_width);
void set_transistor_model_max_width(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type,
const float& max_width);
void set_transistor_model_variation_name(const TechnologyModelId& model_id,
const e_tech_lib_transistor_type& transistor_type,
const std::string& variation_name);
@ -231,6 +236,15 @@ class TechnologyLibrary {
*/
vtr::vector<TechnologyModelId, std::array<float, 2>> transistor_model_min_widths_;
/* The maximum width of a transistor.
* This should be defined by your technology vendor
* The maximum width of a transistor will be used to size your transistors
* If the required width in circuit models in larger then the max width,
* multiple transistor bin will be instanciated.
* For FinFET, the maximum width should be the same as min_width
*/
vtr::vector<TechnologyModelId, std::array<float, 2>> transistor_model_max_widths_;
/* The variation name and id binded to PMOS and NMOS transistor
* We expect users to provide the exact name of variation defined in this technology library
* the name and id will be automatically matched by using function link_model_to_variation()

22
libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
View File

@ -92,6 +92,25 @@ void write_xml_design_technology(std::fstream& fp,
fp << "/>" << "\n";
}
/********************************************************************
* A writer to output the device technology of a circuit model to XML format
*******************************************************************/
static
void write_xml_device_technology(std::fstream& fp,
const char* fname,
const CircuitLibrary& circuit_lib,
const CircuitModelId& model) {
/* Validate the file stream */
openfpga::check_file_stream(fname, fp);
if (!circuit_lib.device_model_name(model).empty()) {
fp << "\t\t\t" << "<device_technology";
write_xml_attribute(fp, "device_model_name", circuit_lib.device_model_name(model).c_str());
/* Finish all the attributes, we can return here */
fp << "/>" << "\n";
}
}
/********************************************************************
* A writer to output a circuit port to XML format
*******************************************************************/
@ -401,6 +420,9 @@ void write_xml_circuit_model(std::fstream& fp,
/* Write the design technology of circuit model */
write_xml_design_technology(fp, fname, circuit_lib, model);
/* Write the device technology of circuit model */
write_xml_device_technology(fp, fname, circuit_lib, model);
/* Write the input buffer information of circuit model,
* only applicable when this circuit model is neither inverter nor buffer
*/

1
libopenfpga/libarchopenfpga/src/write_xml_technology_library.cpp
View File

@ -60,6 +60,7 @@ void write_xml_device_model(std::fstream& fp,
write_xml_attribute(fp, "name", tech_lib.transistor_model_name(device_model, TECH_LIB_TRANSISTOR_PMOS).c_str());
write_xml_attribute(fp, "chan_length", tech_lib.transistor_model_chan_length(device_model, TECH_LIB_TRANSISTOR_PMOS));
write_xml_attribute(fp, "min_width", tech_lib.transistor_model_min_width(device_model, TECH_LIB_TRANSISTOR_PMOS));
write_xml_attribute(fp, "max_width", tech_lib.transistor_model_max_width(device_model, TECH_LIB_TRANSISTOR_PMOS));
if (TechnologyVariationId::INVALID() != tech_lib.transistor_model_variation(device_model, TECH_LIB_TRANSISTOR_PMOS)) {
write_xml_attribute(fp, "variation", tech_lib.variation_name(tech_lib.transistor_model_variation(device_model, TECH_LIB_TRANSISTOR_PMOS)).c_str());
}

13
libopenfpga/libfpgabitstream/src/bitstream_manager.cpp
View File

@ -52,6 +52,13 @@ bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const {
return '1' == bit_values_[bit_id];
}
ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) const {
/* Ensure a valid id */
VTR_ASSERT(true == valid_bit_id(bit_id));
return bit_parent_blocks_[bit_id];
}
std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
@ -140,7 +147,7 @@ std::string BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id
/******************************************************************************
* Public Mutators
******************************************************************************/
ConfigBitId BitstreamManager::add_bit(const bool& bit_value) {
ConfigBitId BitstreamManager::add_bit(const ConfigBlockId& parent_block, const bool& bit_value) {
ConfigBitId bit = ConfigBitId(num_bits_);
/* Add a new bit, and allocate associated data structures */
num_bits_++;
@ -150,6 +157,8 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) {
bit_values_.push_back('0');
}
bit_parent_blocks_.push_back(parent_block);
return bit;
}
@ -234,7 +243,7 @@ void BitstreamManager::add_block_bits(const ConfigBlockId& block,
block_bit_id_lsbs_[block] = num_bits_;
block_bit_lengths_[block] = block_bitstream.size();
for (const bool& bit : block_bitstream) {
add_bit(bit);
add_bit(block, bit);
}
}

6
libopenfpga/libfpgabitstream/src/bitstream_manager.h
View File

@ -119,6 +119,9 @@ class BitstreamManager {
/* Find the value of bitstream */
bool bit_value(const ConfigBitId& bit_id) const;
/* Find the parent block of a configuration bit */
ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const;
/* Find a name of a block */
std::string block_name(const ConfigBlockId& block_id) const;
@ -145,7 +148,7 @@ class BitstreamManager {
public: /* Public Mutators */
/* Add a new configuration bit to the bitstream manager */
ConfigBitId add_bit(const bool& bit_value);
ConfigBitId add_bit(const ConfigBlockId& parent_block, const bool& bit_value);
/* Reserve memory for a number of clocks */
void reserve_blocks(const size_t& num_blocks);
@ -235,6 +238,7 @@ class BitstreamManager {
std::unordered_set<ConfigBitId> invalid_bit_ids_;
/* value of a bit in the Bitstream */
vtr::vector<ConfigBitId, char> bit_values_;
vtr::vector<ConfigBitId, ConfigBlockId> bit_parent_blocks_;
};
} /* end namespace openfpga */

46
openfpga/src/base/openfpga_bitstream.cpp
View File

@ -16,7 +16,8 @@
#include "write_xml_arch_bitstream.h"
#include "build_device_bitstream.h"
#include "fabric_bitstream_writer.h"
#include "write_text_fabric_bitstream.h"
#include "write_xml_fabric_bitstream.h"
#include "build_fabric_bitstream.h"
#include "openfpga_bitstream.h"
@ -65,7 +66,6 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_file = cmd.option("file");
/* Build fabric bitstream here */
openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
@ -73,21 +73,51 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
openfpga_ctx.arch().config_protocol,
cmd_context.option_enable(cmd, opt_verbose));
/* TODO: should identify the error code from internal function execution */
return CMD_EXEC_SUCCESS;
}
/********************************************************************
* A wrapper function to call the write_fabric_bitstream() in FPGA bitstream
*******************************************************************/
int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_file_format = cmd.option("format");
/* Write fabric bitstream if required */
int status = CMD_EXEC_SUCCESS;
if (true == cmd_context.option_enable(cmd, opt_file)) {
std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
/* Create directories */
create_directory(src_dir_path);
std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
/* Create directories */
create_directory(src_dir_path);
/* Check file format requirements */
std::string file_format("plain_text");
if (true == cmd_context.option_enable(cmd, opt_file_format)) {
file_format = cmd_context.option_value(cmd, opt_file_format);
}
if (std::string("xml") == file_format) {
status = write_fabric_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
openfpga_ctx.fabric_bitstream(),
openfpga_ctx.arch().config_protocol,
cmd_context.option_value(cmd, opt_file),
cmd_context.option_enable(cmd, opt_verbose));
} else {
/* By default, output in plain text format */
status = write_fabric_bitstream_to_text_file(openfpga_ctx.bitstream_manager(),
openfpga_ctx.fabric_bitstream(),
openfpga_ctx.arch().config_protocol,
cmd_context.option_value(cmd, opt_file));
cmd_context.option_value(cmd, opt_file),
cmd_context.option_enable(cmd, opt_verbose));
}
/* TODO: should identify the error code from internal function execution */
return status;
}

3
openfpga/src/base/openfpga_bitstream.h
View File

@ -21,6 +21,9 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context);
int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context);
} /* end namespace openfpga */
#endif

71
openfpga/src/base/openfpga_bitstream_command.cpp
View File

@ -41,9 +41,9 @@ ShellCommandId add_openfpga_repack_command(openfpga::Shell<OpenfpgaContext>& she
* - Add command dependency
*******************************************************************/
static
ShellCommandId add_openfpga_arch_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) {
ShellCommandId add_openfpga_build_arch_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("build_architecture_bitstream");
/* Add an option '--write_file' */
@ -75,16 +75,11 @@ ShellCommandId add_openfpga_arch_bitstream_command(openfpga::Shell<OpenfpgaConte
* - Add command dependency
*******************************************************************/
static
ShellCommandId add_openfpga_fabric_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) {
ShellCommandId add_openfpga_build_fabric_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("build_fabric_bitstream");
/* Add an option '--file' in short '-f'*/
CommandOptionId opt_file = shell_cmd.add_option("file", false, "file path to output the fabric bitstream to plain text file");
shell_cmd.set_option_short_name(opt_file, "f");
shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -99,6 +94,40 @@ ShellCommandId add_openfpga_fabric_bitstream_command(openfpga::Shell<OpenfpgaCon
return shell_cmd_id;
}
/********************************************************************
* - Add a command to Shell environment: write_fabric_bitstream
* - Add associated options
* - Add command dependency
*******************************************************************/
static
ShellCommandId add_openfpga_write_fabric_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_fabric_bitstream");
/* Add an option '--file' in short '-f'*/
CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to output the fabric bitstream to plain text file");
shell_cmd.set_option_short_name(opt_file, "f");
shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
/* Add an option '--file_format'*/
CommandOptionId opt_file_format = shell_cmd.add_option("format", false, "file format of fabric bitstream [plain_text|xml]. Default: plain_text");
shell_cmd.set_option_require_value(opt_file_format, openfpga::OPT_STRING);
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
/* Add command 'fabric_bitstream' to the Shell */
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Write the fabric-dependent bitstream to a file");
shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_fabric_bitstream);
/* Add command dependency to the Shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds);
return shell_cmd_id;
}
/********************************************************************
* Top-level function to add all the commands related to FPGA-Bitstream
*******************************************************************/
@ -121,17 +150,25 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
* Command 'build_architecture_bitstream'
*/
/* The 'build_architecture_bitstream' command should NOT be executed before 'repack' */
std::vector<ShellCommandId> cmd_dependency_arch_bitstream;
cmd_dependency_arch_bitstream.push_back(shell_cmd_repack_id);
ShellCommandId shell_cmd_arch_bitstream_id = add_openfpga_arch_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_arch_bitstream);
std::vector<ShellCommandId> cmd_dependency_build_arch_bitstream;
cmd_dependency_build_arch_bitstream.push_back(shell_cmd_repack_id);
ShellCommandId shell_cmd_build_arch_bitstream_id = add_openfpga_build_arch_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_build_arch_bitstream);
/********************************
* Command 'build_fabric_bitstream'
*/
/* The 'build_fabric_bitstream' command should NOT be executed before 'build_architecture_bitstream' */
std::vector<ShellCommandId> cmd_dependency_fabric_bitstream;
cmd_dependency_fabric_bitstream.push_back(shell_cmd_arch_bitstream_id);
add_openfpga_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_fabric_bitstream);
std::vector<ShellCommandId> cmd_dependency_build_fabric_bitstream;
cmd_dependency_build_fabric_bitstream.push_back(shell_cmd_build_arch_bitstream_id);
ShellCommandId shell_cmd_build_fabric_bitstream_id = add_openfpga_build_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_build_fabric_bitstream);
/********************************
* Command 'write_fabric_bitstream'
*/
/* The 'write_fabric_bitstream' command should NOT be executed before 'build_fabric_bitstream' */
std::vector<ShellCommandId> cmd_dependency_write_fabric_bitstream;
cmd_dependency_write_fabric_bitstream.push_back(shell_cmd_build_fabric_bitstream_id);
add_openfpga_write_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_write_fabric_bitstream);
}
} /* end namespace openfpga */

10
openfpga/src/base/openfpga_naming.cpp
View File

@ -238,7 +238,7 @@ std::string generate_routing_block_netlist_name(const std::string& prefix,
std::string generate_routing_block_netlist_name(const std::string& prefix,
const vtr::Point<size_t>& coordinate,
const std::string& postfix) {
return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix );
return std::string( prefix + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") + postfix );
}
/*********************************************************************
@ -968,10 +968,8 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
std::string generate_logical_tile_netlist_name(const std::string& prefix,
const t_pb_graph_node* pb_graph_head,
const std::string& postfix) {
/* This must be the root node */
VTR_ASSERT(true == pb_graph_head->is_root());
/* Add the name of physical block */
std::string module_name = prefix + std::string(pb_graph_head->pb_type->name);
std::string module_name = prefix + generate_physical_block_module_name(pb_graph_head->pb_type);
module_name += postfix;
@ -1183,8 +1181,9 @@ std::string generate_grid_block_instance_name(const std::string& prefix,
module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string());
module_name += std::string("_");
module_name += std::to_string(grid_coord.x());
module_name += std::string("_");
module_name += std::string("__");
module_name += std::to_string(grid_coord.y());
module_name += std::string("_");
return module_name;
}
@ -1244,7 +1243,6 @@ std::string generate_physical_block_module_name(t_pb_type* physical_pb_type) {
return module_name;
}
/*********************************************************************
* Generate the instance name for physical block with a given index
**********************************************************************/

2
openfpga/src/base/openfpga_spice.cpp
View File

@ -39,7 +39,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
int status = CMD_EXEC_SUCCESS;
status = fpga_fabric_spice(openfpga_ctx.module_graph(),
openfpga_ctx.mutable_spice_netlists(),
openfpga_ctx.arch().tech_lib,
openfpga_ctx.arch(),
options);
return status;

12
openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp → openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
View File

@ -1,6 +1,6 @@
/********************************************************************
* This file includes functions that output a fabric-dependent
* bitstream database to files in different formats
* bitstream database to files in plain text
*******************************************************************/
#include <chrono>
#include <ctime>
@ -17,7 +17,7 @@
#include "openfpga_naming.h"
#include "bitstream_manager_utils.h"
#include "fabric_bitstream_writer.h"
#include "write_text_fabric_bitstream.h"
/* begin namespace openfpga */
namespace openfpga {
@ -95,7 +95,8 @@ int write_fabric_config_bit_to_text_file(std::fstream& fp,
int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol,
const std::string& fname) {
const std::string& fname,
const bool& verbose) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
@ -127,6 +128,11 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
/* Close file handler */
fp.close();
VTR_LOGV(verbose,
"Outputted %lu configuration bits to plain text file: %s\n",
fabric_bitstream.bits().size(),
fname.c_str());
return status;
}

7
openfpga/src/fpga_bitstream/fabric_bitstream_writer.h → openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h
View File

@ -1,5 +1,5 @@
#ifndef FABRIC_BITSTREAM_WRITER_H
#define FABRIC_BITSTREAM_WRITER_H
#ifndef WRITE_TEXT_FABRIC_BITSTREAM_H
#define WRITE_TEXT_FABRIC_BITSTREAM_H
/********************************************************************
* Include header files that are required by function declaration
@ -20,7 +20,8 @@ namespace openfpga {
int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol,
const std::string& fname);
const std::string& fname,
const bool& verbose);
} /* end namespace openfpga */

208
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp Normal file
View File

@ -0,0 +1,208 @@
/********************************************************************
* This file includes functions that output a fabric-dependent
* bitstream database to files in XML format
*******************************************************************/
#include <chrono>
#include <ctime>
#include <fstream>
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
/* Headers from archopenfpga library */
#include "openfpga_naming.h"
#include "bitstream_manager_utils.h"
#include "write_xml_fabric_bitstream.h"
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* This function write header information to a bitstream file
*******************************************************************/
static
void write_fabric_bitstream_xml_file_head(std::fstream& fp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "<!--" << std::endl;
fp << "\t- Fabric bitstream" << std::endl;
fp << "\t- Author: Xifan TANG" << std::endl;
fp << "\t- Organization: University of Utah" << std::endl;
fp << "\t- Date: " << std::ctime(&end_time) ;
fp << "-->" << std::endl;
fp << std::endl;
}
/********************************************************************
* Write a configuration bit into a plain text file
* General format
* <bit id="<fabric_bit>" value="<config_bit_value>">
* <hierarchy>
* <!-- configurable memory hierarchy -->
* </hierarchy>
* <!-- address information -->
* ...
* </bit>
* The format depends on the type of configuration protocol
* - Vanilla (standalone): No more information to be included
* - Configuration chain: No more information to be included
* - Memory bank :
* <bl address="<bl_address_value>"/>
* <wl address="<wl_address_value>"/>
* - Frame-based configuration protocol :
* <frame address="<frame_address_value>"/>
*
* Return:
* - 0 if succeed
* - 1 if critical errors occured
*******************************************************************/
static
int write_fabric_config_bit_to_xml_file(std::fstream& fp,
const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const FabricBitId& fabric_bit,
const e_config_protocol_type& config_type) {
if (false == valid_file_stream(fp)) {
return 1;
}
write_tab_to_file(fp, 1);
fp << "<bit id=\"" << size_t(fabric_bit) << "\" ";
fp << "value=\"";
fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit));
fp << "\">\n";
/* Output hierarchy of this parent*/
const ConfigBitId& config_bit = fabric_bitstream.config_bit(fabric_bit);
const ConfigBlockId& config_block = bitstream_manager.bit_parent_block(config_bit);
std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block);
write_tab_to_file(fp, 2);
fp << "<hierarchy>\n";
size_t hierarchy_counter = 0;
for (const ConfigBlockId& temp_block : block_hierarchy) {
write_tab_to_file(fp, 3);
fp << "<instance level=\"" << hierarchy_counter << "\"";
if (0 < bitstream_manager.block_bits(temp_block).size()) {
fp << " width=\"" << bitstream_manager.block_bits(temp_block).size() << "\"";
}
fp << " name=\"" << bitstream_manager.block_name(temp_block) << "\"";
fp << "/>\n";
hierarchy_counter++;
}
write_tab_to_file(fp, 2);
fp << "</hierarchy>\n";
switch (config_type) {
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_SCAN_CHAIN:
break;
case CONFIG_MEM_MEMORY_BANK: {
/* Bit line address */
write_tab_to_file(fp, 2);
fp << "<bl address=\"";
for (const char& addr_bit : fabric_bitstream.bit_bl_address(fabric_bit)) {
fp << addr_bit;
}
fp << "\"/>\n";
write_tab_to_file(fp, 2);
fp << "<wl address=\"";
for (const char& addr_bit : fabric_bitstream.bit_wl_address(fabric_bit)) {
fp << addr_bit;
}
fp << "\"/>\n";
break;
}
case CONFIG_MEM_FRAME_BASED: {
write_tab_to_file(fp, 2);
fp << "<frame address=\"";
for (const char& addr_bit : fabric_bitstream.bit_address(fabric_bit)) {
fp << addr_bit;
}
fp << "\"/>\n";
break;
}
default:
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid configuration protocol type!\n");
return 1;
}
write_tab_to_file(fp, 1);
fp << "</bit>\n";
return 0;
}
/********************************************************************
* Write the fabric bitstream to an XML file
* Notes:
* - This file is designed to be reused by testbench generators, e.g., CocoTB
* - It can NOT be directly loaded to the FPGA fabric
* - It include configurable memory paths in full hierarchy
*
* Return:
* - 0 if succeed
* - 1 if critical errors occured
*******************************************************************/
int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol,
const std::string& fname,
const bool& verbose) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
}
std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.num_bits()) + std::string(" fabric bitstream into xml file '") + fname + std::string("'");
vtr::ScopedStartFinishTimer timer(timer_message);
/* Create the file stream */
std::fstream fp;
fp.open(fname, std::fstream::out | std::fstream::trunc);
check_file_stream(fname.c_str(), fp);
/* Write XML head */
write_fabric_bitstream_xml_file_head(fp);
fp << "<fabric_bitstream>\n";
/* Output fabric bitstream to the file */
int status = 0;
for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) {
status = write_fabric_config_bit_to_xml_file(fp, bitstream_manager,
fabric_bitstream,
fabric_bit,
config_protocol.type());
if (1 == status) {
break;
}
}
/* Print an end to the file here */
fp << "</fabric_bitstream>\n";
/* Close file handler */
fp.close();
VTR_LOGV(verbose,
"Outputted %lu configuration bits to XML file: %s\n",
fabric_bitstream.bits().size(),
fname.c_str());
return status;
}
} /* end namespace openfpga */

28
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.h Normal file
View File

@ -0,0 +1,28 @@
#ifndef WRITE_XML_FABRIC_BITSTREAM_H
#define WRITE_XML_FABRIC_BITSTREAM_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include <string>
#include <vector>
#include "bitstream_manager.h"
#include "fabric_bitstream.h"
#include "config_protocol.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol,
const std::string& fname,
const bool& verbose);
} /* end namespace openfpga */
#endif

5
openfpga/src/fpga_spice/spice_api.cpp
View File

@ -39,7 +39,7 @@ namespace openfpga {
********************************************************************/
int fpga_fabric_spice(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const TechnologyLibrary& tech_lib,
const Arch& openfpga_arch,
const FabricSpiceOption& options) {
vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
@ -71,7 +71,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
int status = CMD_EXEC_SUCCESS;
status = print_spice_submodule(netlist_manager,
tech_lib,
module_manager,
openfpga_arch,
submodule_dir_path);
if (CMD_EXEC_SUCCESS != status) {

4
openfpga/src/fpga_spice/spice_api.h
View File

@ -9,7 +9,7 @@
#include <vector>
#include "netlist_manager.h"
#include "module_manager.h"
#include "technology_library.h"
#include "openfpga_arch.h"
#include "fabric_spice_options.h"
/********************************************************************
@ -21,7 +21,7 @@ namespace openfpga {
int fpga_fabric_spice(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const TechnologyLibrary& tech_lib,
const Arch& openfpga_arch,
const FabricSpiceOption& options);
} /* end namespace openfpga */

984
openfpga/src/fpga_spice/spice_essential_gates.cpp
View File

File diff suppressed because it is too large Load Diff

10
openfpga/src/fpga_spice/spice_essential_gates.h
View File

@ -5,7 +5,10 @@
* Include header files that are required by function declaration
*******************************************************************/
#include <string>
#include <map>
#include "netlist_manager.h"
#include "module_manager.h"
#include "circuit_library.h"
#include "technology_library.h"
/********************************************************************
@ -19,6 +22,13 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
const TechnologyLibrary& tech_lib,
const std::string& submodule_dir);
int print_spice_essential_gates(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const TechnologyLibrary& tech_lib,
const std::map<CircuitModelId, TechnologyModelId>& circuit_tech_binding,
const std::string& submodule_dir);
} /* end namespace openfpga */
#endif

12
openfpga/src/fpga_spice/spice_submodule.cpp
View File

@ -28,15 +28,23 @@ namespace openfpga {
* 6. TODO: Configuration memory blocks
********************************************************************/
int print_spice_submodule(NetlistManager& netlist_manager,
const TechnologyLibrary& tech_lib,
const ModuleManager& module_manager,
const Arch& openfpga_arch,
const std::string& submodule_dir) {
int status = CMD_EXEC_SUCCESS;
status = print_spice_transistor_wrapper(netlist_manager,
tech_lib,
openfpga_arch.tech_lib,
submodule_dir);
status = print_spice_essential_gates(netlist_manager,
module_manager,
openfpga_arch.circuit_lib,
openfpga_arch.tech_lib,
openfpga_arch.circuit_tech_binding,
submodule_dir);
return status;
}

6
openfpga/src/fpga_spice/spice_submodule.h
View File

@ -5,7 +5,8 @@
* Include header files that are required by function declaration
*******************************************************************/
#include "netlist_manager.h"
#include "technology_library.h"
#include "module_manager.h"
#include "openfpga_arch.h"
/********************************************************************
* Function declaration
@ -15,7 +16,8 @@
namespace openfpga {
int print_spice_submodule(NetlistManager& netlist_manager,
const TechnologyLibrary& tech_lib,
const ModuleManager& module_manager,
const Arch& openfpga_arch,
const std::string& submodule_dir);
} /* end namespace openfpga */

39
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -45,14 +45,15 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
/* Create a sensitive list */
fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
fp << "\talways @(" << std::endl;
fp << "\talways @(";
/* Power-gate port first*/
for (const auto& power_gate_port : power_gate_ports) {
/* Skip first comma to dump*/
if (0 < &power_gate_port - &power_gate_ports[0]) {
fp << ",";
/* Only config_enable signal will be considered */
if (false == circuit_lib.port_is_config_enable(power_gate_port)) {
continue;
}
fp << circuit_lib.port_prefix(power_gate_port);
fp << ", ";
}
fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl;
@ -61,6 +62,10 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
/* For the first pin, we skip output comma */
size_t port_cnt = 0;
for (const auto& power_gate_port : power_gate_ports) {
/* Only config_enable signal will be considered */
if (false == circuit_lib.port_is_config_enable(power_gate_port)) {
continue;
}
for (const auto& power_gate_pin : circuit_lib.pins(power_gate_port)) {
if (0 < port_cnt) {
fp << std::endl << "\t\t&&";
@ -70,7 +75,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
/* Power-gated signal are disable during operating, enabled during configuration,
* Therefore, we need to reverse them here
*/
if (0 == circuit_lib.port_default_value(power_gate_port)) {
if (1 == circuit_lib.port_default_value(power_gate_port)) {
fp << "~";
}
@ -161,30 +166,6 @@ void print_verilog_invbuf_module(const ModuleManager& module_manager,
VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
/* TODO: move the check codes to check_circuit_library.h */
/* If the circuit model is power-gated, we need to find at least one global config_enable signals */
if (true == circuit_lib.is_power_gated(circuit_model)) {
/* Check all the ports we have are good for a power-gated circuit model */
size_t num_err = 0;
/* We need at least one global port */
if (0 == global_ports.size()) {
num_err++;
}
/* All the global ports should be config_enable */
for (const auto& port : global_ports) {
if (false == circuit_lib.port_is_config_enable(port)) {
num_err++;
}
}
/* Report errors if there are any */
if (0 < num_err) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
circuit_lib.model_name(circuit_model).c_str());
exit(1);
}
}
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));

112
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -63,14 +63,12 @@ namespace openfpga {
*
*******************************************************************/
static
void print_verilog_primitive_block(std::fstream& fp,
void print_verilog_primitive_block(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& subckt_dir,
t_pb_graph_node* primitive_pb_graph_node,
const bool& use_explicit_mapping,
const bool& verbose) {
/* Ensure a valid file handler */
VTR_ASSERT(true == valid_file_stream(fp));
/* Ensure a valid pb_graph_node */
if (nullptr == primitive_pb_graph_node) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -78,6 +76,24 @@ void print_verilog_primitive_block(std::fstream& fp,
exit(1);
}
/* Give a name to the Verilog netlist */
/* Create the file name for Verilog */
std::string verilog_fname(subckt_dir
+ generate_logical_tile_netlist_name(std::string(), primitive_pb_graph_node, std::string(VERILOG_NETLIST_FILE_POSTFIX))
);
VTR_LOG("Writing Verilog netlist '%s' for primitive pb_type '%s' ...",
verilog_fname.c_str(), primitive_pb_graph_node->pb_type->name);
VTR_LOGV(verbose, "\n");
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name)));
/* Generate the module name for this primitive pb_graph_node*/
std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
@ -93,8 +109,13 @@ void print_verilog_primitive_block(std::fstream& fp,
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping);
/* Add an empty line as a splitter */
fp << std::endl;
/* Close file handler */
fp.close();
/* Add fname to the netlist name list */
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
VTR_LOGV(verbose, "Done\n");
}
@ -115,14 +136,13 @@ void print_verilog_primitive_block(std::fstream& fp,
* to its parent in module manager
*******************************************************************/
static
void rec_print_verilog_logical_tile(std::fstream& fp,
void rec_print_verilog_logical_tile(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const std::string& subckt_dir,
t_pb_graph_node* physical_pb_graph_node,
const bool& use_explicit_mapping,
const bool& verbose) {
/* Check the file handler*/
VTR_ASSERT(true == valid_file_stream(fp));
/* Check cur_pb_graph_node*/
if (nullptr == physical_pb_graph_node) {
@ -143,8 +163,9 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
if (false == is_primitive_pb_type(physical_pb_type)) {
for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
/* Go recursive to visit the children */
rec_print_verilog_logical_tile(fp,
module_manager, device_annotation,
rec_print_verilog_logical_tile(netlist_manager,
module_manager, device_annotation,
subckt_dir,
&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
use_explicit_mapping,
verbose);
@ -156,7 +177,9 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
* explict port mapping. This aims to avoid any port sequence issues!!!
*/
if (true == is_primitive_pb_type(physical_pb_type)) {
print_verilog_primitive_block(fp, module_manager,
print_verilog_primitive_block(netlist_manager,
module_manager,
subckt_dir,
physical_pb_graph_node,
true,
verbose);
@ -164,6 +187,24 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
return;
}
/* Give a name to the Verilog netlist */
/* Create the file name for Verilog */
std::string verilog_fname(subckt_dir
+ generate_logical_tile_netlist_name(std::string(), physical_pb_graph_node, std::string(VERILOG_NETLIST_FILE_POSTFIX))
);
VTR_LOG("Writing Verilog netlist '%s' for pb_type '%s' ...",
verilog_fname.c_str(), physical_pb_type->name);
VTR_LOGV(verbose, "\n");
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for pb_type: " + std::string(physical_pb_type->name)));
/* Generate the name of the Verilog module for this pb_type */
std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
@ -172,7 +213,7 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
VTR_LOGV(verbose,
"Writing Verilog codes of logical tile block '%s'...",
"Writing Verilog codes of pb_type '%s'...",
module_manager.module_name(pb_module).c_str());
/* Comment lines */
@ -183,8 +224,13 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
/* Add an empty line as a splitter */
fp << std::endl;
/* Close file handler */
fp.close();
/* Add fname to the netlist name list */
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
VTR_LOGV(verbose, "Done\n");
}
@ -201,23 +247,10 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
t_pb_graph_node* pb_graph_head,
const bool& use_explicit_mapping,
const bool& verbose) {
/* Give a name to the Verilog netlist */
/* Create the file name for Verilog */
std::string verilog_fname(subckt_dir
+ generate_logical_tile_netlist_name(std::string(LOGICAL_MODULE_VERILOG_FILE_NAME_PREFIX), pb_graph_head, std::string(VERILOG_NETLIST_FILE_POSTFIX))
);
VTR_LOG("Writing Verilog netlist '%s' for logic tile '%s' ...",
verilog_fname.c_str(), pb_graph_head->pb_type->name);
VTR_LOGV(verbose, "\n");
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]"));
VTR_LOG("Writing Verilog netlists for logic tile '%s' ...",
pb_graph_head->pb_type->name);
VTR_LOG("\n");
/* Print Verilog modules for all the pb_types/pb_graph_nodes
* use a Depth-First Search Algorithm to print the sub-modules
@ -226,23 +259,14 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
* to its parent in module manager
*/
/* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
rec_print_verilog_logical_tile(fp, module_manager,
rec_print_verilog_logical_tile(netlist_manager,
module_manager,
device_annotation,
subckt_dir,
pb_graph_head,
use_explicit_mapping,
verbose);
/* Add an empty line as a splitter */
fp << std::endl;
/* Close file handler */
fp.close();
/* Add fname to the netlist name list */
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
VTR_LOG("Done\n");
VTR_LOG("\n");
}
@ -270,7 +294,7 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
/* Give a name to the Verilog netlist */
/* Create the file name for Verilog */
std::string verilog_fname(subckt_dir
+ generate_grid_block_netlist_name(std::string(phy_block_type->name),
+ generate_grid_block_netlist_name(std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name),
is_io_type(phy_block_type),
border_side,
std::string(VERILOG_NETLIST_FILE_POSTFIX))

9
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1154,17 +1154,18 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
/* Attention: when the fast configuration is enabled, we will start from the first bit '1'
* This requires a reset signal (as we forced in the first clock cycle)
*/
bool first_bit_one = false;
bool start_config = false;
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
first_bit_one = true;
if ( (false == start_config)
&& (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) {
start_config = true;
}
/* In fast configuration mode, we do not output anything
* until we have to (the first bit '1' detected)
*/
if ( (true == fast_configuration)
&& (false == first_bit_one)) {
&& (false == start_config)) {
continue;
}

58
openfpga/src/utils/circuit_library_utils.cpp
View File

@ -287,4 +287,62 @@ bool check_configurable_memory_circuit_model(const e_config_protocol_type& confi
return (0 == num_err);
}
/************************************************************************
* Try to find the enable port control power-gate for a power-gated circuit model
* We will return the first port that meet the requirement:
* - a global port
* - its function is labelled as config_enable
* - default value is 0
* Return invalid id if not found
***********************************************************************/
CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
/* Try to find an ENABLE port from the global ports */
CircuitPortId en_port = CircuitPortId::INVALID();
for (const auto& port : global_ports) {
/* Focus on config_enable ports which are power-gate control signals */
if (false == circuit_lib.port_is_config_enable(port)) {
continue;
}
if (1 == circuit_lib.port_default_value(port)) {
en_port = port;
break;
}
}
return en_port;
}
/************************************************************************
* Try to find the enableB port control power-gate for a power-gated circuit model
* We will return the first port that meet the requirement:
* - a global port
* - its function is labelled as config_enable
* - default value is 1
* Return invalid id if not found
***********************************************************************/
CircuitPortId find_circuit_model_power_gate_enb_port(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
CircuitPortId enb_port = CircuitPortId::INVALID();
VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
/* Try to find an ENABLE_B port from the global ports */
for (const auto& port : global_ports) {
/* Focus on config_enable ports which are power-gate control signals */
if (false == circuit_lib.port_is_config_enable(port)) {
continue;
}
if (0 == circuit_lib.port_default_value(port)) {
enb_port = port;
break;
}
}
return enb_port;
}
} /* end namespace openfpga */

6
openfpga/src/utils/circuit_library_utils.h
View File

@ -43,6 +43,12 @@ bool check_configurable_memory_circuit_model(const e_config_protocol_type& confi
const CircuitLibrary& circuit_lib,
const CircuitModelId& config_mem_circuit_model);
CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
CircuitPortId find_circuit_model_power_gate_enb_port(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
} /* end namespace openfpga */
#endif

7
openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
View File

@ -37,10 +37,13 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist

7
openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
View File

@ -37,10 +37,13 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist

5
openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
View File

@ -37,11 +37,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

7
openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
View File

@ -37,10 +37,13 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist

5
openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
View File

@ -37,11 +37,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

5
openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
View File

@ -37,11 +37,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

8
openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga
View File

@ -35,10 +35,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Finish and exit OpenFPGA
exit

5
openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga
View File

@ -40,11 +40,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

5
openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga
View File

@ -40,11 +40,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

35
openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga Normal file
View File

@ -0,0 +1,35 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_spice --file ./SPICE --verbose
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

5
openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
View File

@ -37,11 +37,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream --format xml
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches

5
openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
View File

@ -37,11 +37,14 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

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# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Read external bitstream from a file which will overwrite the VPR results
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose \
--read_file ${OPENFPGA_EXTERNAL_ARCH_BITSTREAM_FILE} \
--write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

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module FSM_hour(
input wire rst,
input wire clk,
input wire [5:0] hour_in,
input wire hour_in_load,
input wire [5:0] min_count,
input wire [5:0] sec_count,
output reg [5:0] hour_out);
reg [2:0] ps, ns;
wire [5:0] hour_data_add;
reg [5:0] hour_data;
reg [5:0] hour_ps, hour_ns;
reg [1:0] hour_sel;
wire hour_count;
always@(posedge clk)
begin
if(rst) ps <= 3'd0;
else ps <= ns;
end
always@(posedge clk)
begin
if(rst) hour_ps <= 6'd0;
else hour_ps <= hour_ns;
end
always@(*)
begin
hour_sel = 2'd0;
case(ps)
3'd0: begin
ns = 3'd1;
end
3'd1: begin
if(hour_in_load) begin
hour_sel = 2'd1;
hour_out = hour_data;
ns = 3'd2;
hour_ns = hour_data;
end
else ns = 3'd1;
end
3'd2: begin
if(hour_count == 1'd1) begin
if(hour_data == 6'd59) begin
hour_out = hour_data;
ns = 3'd2;
hour_ns = 6'd0;
end
else begin
hour_out = hour_data;
ns = 3'd2;
hour_ns = hour_data_add;
end
end
else begin
hour_out = hour_data;
hour_ns = hour_data;
ns = 3'd2;
end
end
default: begin
ns = 3'd0;
end
endcase
end
assign hour_data_add = hour_data + 1;
assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0;
always@(*)
begin
case(hour_sel)
2'd0: hour_data = hour_ps;
2'd1: hour_data = hour_in;
endcase
end
endmodule

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module FSM_minute(
input wire rst,
input wire clk,
input wire [5:0] min_in,
input wire min_in_load,
input wire [5:0] sec_count,
output reg [5:0] min_out);
reg [2:0] ps, ns;
wire [5:0] min_data_add;
reg [5:0] min_data;
reg [5:0] min_ps, min_ns;
reg [1:0] min_sel;
wire min_count;
always@(posedge clk)
begin
if(rst) ps <= 3'd0;
else ps <= ns;
end
always@(posedge clk)
begin
if(rst) min_ps <= 6'd0;
else min_ps <= min_ns;
end
always@(*)
begin
min_sel = 2'd0;
case(ps)
3'd0: begin
ns = 3'd1;
end
3'd1: begin
if(min_in_load) begin
min_sel = 2'd1;
min_out = min_data;
ns = 3'd2;
min_ns = min_data;
end
else ns = 3'd1;
end
3'd2: begin
if(min_count == 1'd1) begin
if(min_data == 6'd59) begin
min_out = min_data;
ns = 3'd2;
min_ns = 6'd0;
end
else begin
min_out = min_data;
ns = 3'd2;
min_ns = min_data_add;
end
end
else begin
min_out = min_data;
min_ns = min_data;
ns = 3'd2;
end
end
default: begin
ns = 3'd0;
end
endcase
end
assign min_data_add = min_data + 1;
assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0;
always@(*)
begin
case(min_sel)
2'd0: min_data = min_ps;
2'd1: min_data = min_in;
endcase
end
endmodule

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module FSM_second(
input wire rst,
input wire clk,
input wire [5:0] sec_in,
input wire sec_in_load,
output reg [5:0] sec_out);
reg [2:0] ps, ns;
wire [5:0] sec_data_add;
reg [5:0] sec_data;
reg [5:0] sec_ps, sec_ns;
reg [1:0] sec_sel;
always@(posedge clk)
begin
if(rst) ps <= 3'd0;
else ps <= ns;
end
always@(posedge clk)
begin
if(rst) sec_ps <= 6'd0;
else sec_ps <= sec_ns;
end
always@(*)
begin
sec_sel = 2'd0;
case(ps)
3'd0: begin
ns = 3'd1;
end
3'd1: begin
if(sec_in_load) begin
sec_sel = 2'd1;
sec_out = sec_data;
ns = 3'd2;
sec_ns = sec_data_add;
end
else ns = 3'd1;
end
3'd2: begin
if(sec_data == 6'd59) begin
sec_out = sec_data;
ns = 3'd2;
sec_ns = 6'd0;
end
else begin
sec_out = sec_data;
ns = 3'd2;
sec_ns = sec_data_add;
end
end
default: begin
ns = 3'd0;
end
endcase
end
assign sec_data_add = sec_data + 1;
always@(*)
begin
case(sec_sel)
2'd0: sec_data = sec_ps;
2'd1: sec_data = sec_in;
endcase
end
endmodule

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module FSM_three_tb;
reg rst;
reg clk;
reg [5:0] sec_in, min_in, hour_in;
reg load_in;
wire [5:0] sec_out, min_out, hour_out;
FSM_top FSM_1(
.rst(rst),
.clk(clk),
.sec_in(sec_in),
.load_in(load_in),
.sec_out(sec_out),
.min_in(min_in),
.min_out(min_out),
.hour_in(hour_in),
.hour_out(hour_out));
initial begin
#0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5;
#100 rst = 1'd0;
#50 load_in = 1'd0;
end
always begin
#10 clk = ~clk;
end
initial begin
#100000 $stop;
end
endmodule

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module FSM_top(
input wire rst,
input wire clk,
input wire load_in,
input wire [5:0] sec_in,
input wire [5:0] min_in,
input wire [5:0] hour_in,
output wire [5:0] sec_out,
output wire [5:0] min_out,
output wire [5:0] hour_out
);
FSM_second FSM_sec(
.rst(rst),
.clk(clk),
.sec_in(sec_in),
.sec_in_load(load_in),
.sec_out(sec_out));
FSM_minute FSM_min(
.rst(rst),
.clk(clk),
.min_in(min_in),
.min_in_load(load_in),
.sec_count(sec_out),
.min_out(min_out));
FSM_hour FSM_hr(
.rst(rst),
.clk(clk),
.hour_in(hour_in),
.hour_in_load(load_in),
.min_count(min_out),
.hour_out(hour_out),
.sec_count(sec_out));
endmodule

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module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
output zero_flag_out;
output reg [7:0]alu_out;
input [7:0]Reg_Y_in,Bus_1_in;
input [7:0]IR_code;
wire [3:0]opcode=IR_code[7:4];
always@(*)
begin
case(opcode)
1: alu_out=Reg_Y_in+Bus_1_in;
2: alu_out=Bus_1_in+~(Reg_Y_in)+1;
3: alu_out=Reg_Y_in&(Bus_1_in);
4: alu_out=~(Bus_1_in);
default:alu_out=8'b0;
endcase
end
assign zero_flag_out=~|alu_out;
endmodule

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module Controller(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,write,
zero,instruction,nclk,rst);
//狀態
parameter S_idle=0,S_fet1=1,S_fet2=2,S_dec=3,
S_ex1=4,S_rd1=5,S_rd2=6,S_wr1=7,S_wr2=8,
S_br1=9,S_br2=10,S_halt=11;
//指令
parameter NOP=0,ADD=1,SUB=2,AND=3,NOT=4,
RD=5,WR=6,BR=7,BRZ=8;
output reg L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
L_IR,L_ADD_R,L_R_Y,L_R_Z,write;
output reg[2:0]Sel_Bus1;
output reg [1:0]Sel_Bus2;
input zero,nclk,rst;
input [7:0]instruction;
reg [15:0]Con_out;
reg [3:0]PS,NS;
reg err_flag;
wire [1:0]src=instruction[3:2];
wire [1:0]dest=instruction[1:0];
wire [3:0]opcode=instruction[7:4];
always@(posedge nclk)
begin
if(rst==1)PS<=0;
else PS<=NS;
end
always@(PS,opcode,src,dest,zero)
begin
L_R0=0;
L_R1=0;
L_R2=0;
L_R3=0;
L_PC=0;
Inc_PC=0;
Sel_Bus1=0;
L_IR=0;
L_ADD_R=0;
L_R_Y=0;
L_R_Z=0;
Sel_Bus2=0;
write=0;
err_flag=0;
case(PS)
S_idle: NS=S_fet1;
S_fet1: begin
NS=S_fet2;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=2'b01;//Sel_Bus1
L_ADD_R=1;
end
S_fet2: begin
NS=S_dec;
Sel_Bus2=2'b10;//Sel_Mem
L_IR=1;
Inc_PC=1;
end
S_dec: begin
case(opcode)
NOP:NS=S_fet1;
ADD,SUB,AND:begin
NS=S_ex1;
Sel_Bus2=2'b01;//Sel_Bus1
L_R_Y=1;
case(src)
0: Sel_Bus1=3'b000;//R0
1: Sel_Bus1=3'b001;//R1
2: Sel_Bus1=3'b010;//R2
3: Sel_Bus1=3'b011;//R3
default err_flag=1;
endcase
end//ADD,SUB,AND
NOT:begin
NS=S_fet1;
L_R_Z=1;
Sel_Bus2=2'b00;//Sel_ALU
case(src)
0: Sel_Bus1=3'b000;//R0
1: Sel_Bus1=3'b001;//R1
2: Sel_Bus1=3'b010;//R2
3: Sel_Bus1=3'b011;//R3
default err_flag=1;
endcase
case(dest)
0: L_R0=1;
1: L_R1=1;
2: L_R2=1;
3: L_R3=1;
default err_flag=1;
endcase
end//NOT
RD: begin
NS=S_rd1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end//RD
WR: begin
NS=S_wr1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end//WR
BR: begin
NS=S_br1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end//BR
BRZ:begin
if(zero==1)begin
NS=S_br1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end
else begin
NS=S_fet1;
Inc_PC=1;
end
end//BRZ
default NS=S_halt;
endcase//opcode
end
S_ex1: begin
NS=S_fet1;
L_R_Z=1;
Sel_Bus2=2'b00;//Sel_ALU
case(dest)
0: begin Sel_Bus1=3'b000;L_R0=1;end
1: begin Sel_Bus1=3'b001;L_R1=1;end
2: begin Sel_Bus1=3'b010;L_R2=1;end
3: begin Sel_Bus1=3'b011;L_R3=1;end
default err_flag=1;
endcase
end
S_rd1: begin
NS=S_rd2;
Inc_PC=1;
Sel_Bus2=2'b10;//Sel_Mem
L_ADD_R=1;
end
S_wr1: begin
NS=S_wr2;
Inc_PC=1;
Sel_Bus2=2'b10;//Sel_Mem
L_ADD_R=1;
end
S_rd2: begin
NS=S_fet1;
Sel_Bus2=2'b10;//Sel_Mem
case(dest)
0: L_R0=1;
1: L_R1=1;
2: L_R2=1;
3: L_R3=1;
default err_flag=1;
endcase
end
S_wr2: begin
NS=S_fet1;
write=1;
case(src)
0: Sel_Bus1=3'b000;//R0
1: Sel_Bus1=3'b001;//R1
2: Sel_Bus1=3'b010;//R2
3: Sel_Bus1=3'b011;//R3
default err_flag=1;
endcase
end
S_br1: begin
NS=S_br2;
Sel_Bus2=2'b10;//Sel_Mem
L_ADD_R=1;
end
S_br2: begin
NS=S_fet1;
Sel_Bus2=2'b10;//Sel_Mem
L_PC=1;
end
S_halt: NS=S_halt;
default NS=S_idle;
endcase
end
endmodule

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module IR(IR_out,IR_in,load,clk,rst);
output reg [7:0]IR_out;
input [7:0]IR_in;
input load,clk,rst;
always@(posedge clk)
begin
if(rst==1)IR_out<=8'b0;
else if(load==1)IR_out<=IR_in;
end
endmodule

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module Memory(Data_out,Address);
output [7:0]Data_out;
input [7:0]Address;
reg [7:0]mem[255:0];
assign Data_out=mem[Address];
always@(Address)
begin
case(Address)
//opcode_src_dest
//NOP
0: mem[Address]=8'b0000_00_00;
//rd 00 10 //Read MEM[130] to R2
1: mem[Address]=8'b0101_00_10; //Instruction
2: mem[Address]=130; //Address
//rd 00 11 //Read MEM[131] to R3
3: mem[Address]=8'b0101_00_11; //Instruction
4: mem[Address]=131; //Address
//rd 00 01 //Read MEM[128] to R1
5: mem[Address]=8'b0101_00_01; //Instruction
6: mem[Address]=128; //Address
//rd 00 00 //Read MEM[129] to R0
7: mem[Address]=8'b0101_00_00; //Instruction
8: mem[Address]=129; //Address
//Sub 00 01 //Sub R1-R0 to R1
9: mem[Address]=8'b0010_00_01; //Instruction
//BRZ 00 00
10: mem[Address]=8'b1000_00_00; //Instruction
11: mem[Address]=134; //Address
//Add 10 11 //Add R2+R3 to R3
12: mem[Address]=8'b00011011;
//BR
13: mem[Address]=8'b01110011; //Instruction
14: mem[Address]=140; //Address
128:mem[Address]=6;
129:mem[Address]=1;
130:mem[Address]=2;
131:mem[Address]=0;
134:mem[Address]=139; //Address
135:mem[Address]=0;
//HAL
139:mem[Address]=8'b1111_00_00; //Instruction
140:mem[Address]=9; //Address
default mem[Address]=8'bx;
endcase
end
endmodule

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module Mux_31(Y,A0,A1,A2,sel);
output [7:0]Y;
input [7:0]A2,A1,A0;
input [1:0]sel;
reg [7:0]Y;
always@(*)
begin
case(sel)
0: Y=A0;
1: Y=A1;
2: Y=A2;
default:Y=8'bz;
endcase
end
endmodule

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module Mux_51(Y,A0,A1,A2,A3,A4,sel);
output [7:0]Y;
input [7:0]A4,A3,A2,A1,A0;
input [2:0]sel;
reg [7:0]Y;
always@(*)
begin
case(sel)
0: Y=A0;
1: Y=A1;
2: Y=A2;
3: Y=A3;
4: Y=A4;
default:Y=8'bx;
endcase
end
endmodule

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module PC(PC_out,PC_in,load,inc,clk,rst);
output [7:0]PC_out;
input [7:0]PC_in;
input load,inc,clk,rst;
reg [7:0]PC_out;
always@(posedge clk)
begin
if(rst==1)PC_out<=8'b0;
else if(load==1)PC_out<=PC_in;
else if(inc==1)PC_out<=PC_out+8'b00000001;
end
endmodule

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module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
output [7:0]bus_1_out;
input clk,rst;
output [7:0]Reg_R0_out;
output [7:0]Reg_R1_out;
output [7:0]Reg_R2_out;
output [7:0]Reg_R3_out;
wire [7:0]bus_1_out,MEMAddress;
wire clk,rst;
wire [7:0]MEMdataout;
wire [7:0]Reg_R0_out;
wire [7:0]Reg_R1_out;
wire [7:0]Reg_R2_out;
wire [7:0]Reg_R3_out;
RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
Memory MEM(MEMdataout,MEMAddress);
endmodule

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module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
output [7:0]bus_1_out,MEMAddress;
input clk,rst;
input [7:0]MEMdataout;
output [7:0]Reg_R0_out;
output [7:0]Reg_R1_out;
output [7:0]Reg_R2_out;
output [7:0]Reg_R3_out;
wire [7:0]BUS_2,BUS_1,MEMAddress;
wire [7:0]alu_out;
wire [7:0]MEMdataout;
wire [7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out;
wire [7:0]IR_out;
wire zero_flag_out;
wire [2:0]Sel_Bus1;
wire [1:0]Sel_Bus2;
wire L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero;
assign bus_1_out=BUS_1;
assign bus_2_out=BUS_2;
Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst);
//module PC(PC_out,PC_in,load,inc,clk,rst);
PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst);
//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
ALU Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out);
//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite);
//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite);
//module Mux_31(Y,A0,A1,A2,sel);
Mux_31 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2);
//module Reg_1bit(Q,D,load,clk,rst);
Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst);
//module Reg_8bit(Q,D,load,clk,rst);
Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst);
Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst);
//R0~R3
Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst);
Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst);
Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst);
Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst);
//module Mux_51(Y,A0,A1,A2,A3,A4,sel);
Mux_51 Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1);
//module IR(IR_out,IR_in,load,clk,rst);
IR Instruction_Register(IR_out,BUS_2,L_IR,clk,rst);
endmodule

53
openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v Normal file
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`timescale 1ns/1ns
module RISC_testbench;
wire [7:0]bus_1_out;
reg clk,rst;
wire [7:0]Reg_R0_out;
wire [7:0]Reg_R1_out;
wire [7:0]Reg_R2_out;
wire [7:0]Reg_R3_out;
/* wire [7:0]MEMAddress;
wire [7:0]MEMdataout;
wire MEMwrite; */
/* assign MEMAddress = top.MEMAddress;
assign MEMdataout = top.MEMdataout;
assign MEMwrite = top.MEMwrite; */
RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
always#20 clk=~clk;
initial
begin
clk=0;rst=1;
#30 rst=0;
#6000 $stop;
end
/* //----------
integer fp;
initial
begin
fp = $fopen("RISC_xa.vec");
$fdisplay(fp, "radix 1 1 44 44 44 44 44 1 44 44");
$fdisplay(fp, "vname clk rst Reg_R0_out[[7:0]] Reg_R1_out[[7:0]] Reg_R2_out[[7:0]] Reg_R3_out[[7:0]] bus_1_out[[7:0]] MEMwrite MEMAddress MEMdataout");
$fdisplay(fp, " io i i oo oo oo oo oo o oo ii");
$fdisplay(fp, "slope 0.3");
$fdisplay(fp, " vih 3.3");
$fdisplay(fp, " vil 0");
$fdisplay(fp, "tunit ns");
end
always@(clk)
begin
$fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout);
end
//---------- */
endmodule

16
openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v Normal file
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module Reg_1bit(Q,D,load,clk,rst);
output Q;
input D;
input load,clk,rst;
reg Q;
always@(posedge clk)
begin
if(rst==1)Q<=0;
else if(load==1)Q<=D;
end
endmodule

16
openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v Normal file
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module Reg_8bit(Q,D,load,clk,rst);
output [7:0]Q;
input [7:0]D;
input load,clk,rst;
reg [7:0]Q;
always@(posedge clk)
begin
if(rst==1)Q<=8'b0;
else if(load==1)Q<=D;
end
endmodule

19
openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v Normal file
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module ACC(
output [7:0] acc_out1,
output [7:0] acc_out2,
input [7:0] acc_in,
input la_,
input clk,
input clr_
);
reg [7:0] q;
always @(posedge clk)
if (~clr_) q <= 8'b0;
else if(~la_) q <= acc_in;
assign acc_out1 = q;
assign acc_out2 = q;
endmodule

13
openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v Normal file
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module ADDSUB(
output [7:0] ADDSUB_out,
input [7:0] ADDSUB_in1,
input [7:0] ADDSUB_in2,
input su
);
wire [7:0] d;
assign d = su ? ADDSUB_in1 - ADDSUB_in2 : ADDSUB_in1 + ADDSUB_in2;
assign ADDSUB_out = d;
endmodule

13
openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v Normal file
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module BRegister(
output reg [7:0] BRegister_out,
input [7:0] BRegister_in,
input lb_,
input clk,
input clr_
);
always @(posedge clk)
if(~clr_) BRegister_out <= 8'b0;
else if(~lb_) BRegister_out <= BRegister_in;
endmodule

119
openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v Normal file
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module Controller(
output reg [11:0] control_signals,
input [3:0] opcode,
input clk,
input clr_
);
reg [3:0] ps, ns;
always @(posedge clk)
begin
if(~clr_) ps <= 4'd0;
else ps <= ns;
end
always @(*)
begin
case(ps)
0:
begin
control_signals = 12'h3e3;
ns = 4'd1;
end
1: //T1
begin
control_signals = 12'h5e3;
ns = 4'd2;
end
2: //T2
begin
// control_signals = 12'hbe3;
control_signals = 12'h863;
ns = 4'd3;
end
3: //T3
begin
// control_signals = 12'h263;
control_signals = 12'h3e3;
if(opcode == 4'd0) //LDA
ns = 4'd4;
else if(opcode == 4'd1) //ADD
ns = 4'd6;
else if(opcode == 4'd2) //SUB
ns = 4'd9;
else if(opcode == 4'd14) //OUT
ns = 4'd12;
else if(opcode == 4'd15) //HLT
ns = 4'd13;
end
4: //LDA
begin
control_signals = 12'h1a3;
ns = 4'd5;
end
5: //LDA
begin
control_signals = 12'h2c3;
ns = 4'd1;
end
6: //ADD
begin
control_signals = 12'h1a3;
ns = 4'd7;
end
7: //ADD
begin
control_signals = 12'h2e1;
ns = 4'd8;
end
8: //ADD
begin
control_signals = 12'h3c7;
ns = 4'd1;
end
9: //SUB
begin
control_signals = 12'h1a3;
ns = 4'd10;
end
10: //SUB
begin
control_signals = 12'h2e1;
ns = 4'd11;
end
11: //SUB
begin
control_signals = 12'h3cf;
ns = 4'd1;
end
12: //OUT
begin
control_signals = 12'h3f2;
ns = 4'd1;
end
13: //HLT
ns = 4'd13;
default:
begin
ns = 4'd0;
control_signals = 12'h3e3;
end
endcase
end
endmodule

21
openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v Normal file
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module IR(
output [7:4] opcode,
output [3:0] oprand,
input wire [7:0] IR_in,
input li_,
input clk,
input clr_
);
reg [7:0] q;
always @(posedge clk)
begin
if(~clr_) q <=8'b0;
else if(~li_) q <= IR_in;
end
assign opcode = q[7:4];
assign oprand = q[3:0];
endmodule

13
openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v Normal file
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module MAR(
output reg [3:0] mar_out,
input wire [3:0] mar_in,
input lm_,
input clk,
input clr_
);
always @(posedge clk)
if(~clr_) mar_out <= 4'b0;
else if(~lm_) mar_out <= mar_in;
endmodule

13
openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v Normal file
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module OutputRegister(
output reg [7:0] OutputRegister_out,
input [7:0] OutputRegister_in,
input lo_,
input clk,
input clr_
);
always @(posedge clk)
if(~clr_) OutputRegister_out <= 8'b0;
else if(~lo_) OutputRegister_out <= OutputRegister_in;
endmodule

15
openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v Normal file
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module PC(
output reg [3:0] pc_out,
input cp,
input clk,
input clr_
);
always @(posedge clk)
begin
if(~clr_) pc_out <= 0;
else if (cp) pc_out <= pc_out + 1;
end
endmodule

26
openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v Normal file
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module ROM(
output reg [7:0] rom_out,
input [3:0] rom_in
);
always @(*)
begin
rom_out = 8'bx;
case(rom_in)
4'b0000: rom_out = 8'b0000_1001; //LDA
4'b0001: rom_out = 8'b0001_1010; //ADD
4'b0010: rom_out = 8'b0001_1011; //ADD
4'b0011: rom_out = 8'b0010_1100; //SUB
4'b0100: rom_out = 8'b1110_xxxx; //OUT
4'b0101: rom_out = 8'b1111_xxxx; //HLT
4'b0110: rom_out = 8'bxxxx_xxxx;
4'b0111: rom_out = 8'bxxxx_xxxx;
4'b1000: rom_out = 8'bxxxx_xxxx;
4'b1001: rom_out = 8'b0001_0000;
4'b1010: rom_out = 8'b0001_0100;
4'b1011: rom_out = 8'b0001_1000;
4'b1100: rom_out = 8'b0010_0000;
endcase
end
endmodule

100
openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v Normal file
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module SAPone(
output wire [7:0] SAP_out,
output wire [11:0] con,
output reg [7:0] bus,
input clk,
input clr_
);
wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_;
wire [7:0] acc_out2, BRegister_out, OutputRegister_out;
wire [3:0] IR_out, mar_out;
wire [4:0] bus_sel;
wire [3:0] pc_out, oprand;
wire [7:0] rom_out, acc_out1, ADDSUB_out;
assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con;
assign bus_sel = {ep, ce_, ei_, ea, eu};
always@(*)
begin
case(bus_sel)
5'b11100: bus[3:0] = pc_out;
5'b00100: bus[7:0] = rom_out;
5'b01000: bus[3:0] = oprand;
5'b01110: bus[7:0] = acc_out1;
5'b01101: bus[7:0] = ADDSUB_out;
default: bus[7:0] = 8'bx;
endcase
end
PC pc1(
.pc_out(pc_out),
.cp(cp),
.clk(clk),
.clr_(clr_)
);
MAR mar1(
.mar_out(mar_out),
.mar_in(bus[3:0]),
.lm_(lm_),
.clk(clk),
.clr_(clr_)
);
ROM roml(
.rom_out(rom_out),
.rom_in(mar_out)
);
IR ir1(
.opcode(IR_out),
.oprand(oprand),
.IR_in(bus[7:0]),
.li_(li_),
.clk(clk),
.clr_(clr_)
);
Controller cont1(
.control_signals(con),
.opcode(IR_out),
.clk(clk),
.clr_(clr_)
);
ACC acc1(
.acc_out1(acc_out1),
.acc_out2(acc_out2),
.acc_in(bus[7:0]),
.la_(la_),
.clk(clk),
.clr_(clr_)
);
ADDSUB addsub1(
.ADDSUB_out(ADDSUB_out),
.ADDSUB_in1(acc_out2),
.ADDSUB_in2(BRegister_out),
.su(su)
);
BRegister bregister1(
.BRegister_out(BRegister_out),
.BRegister_in(bus[7:0]),
.lb_(lb_),
.clk(clk),
.clr_(clr_)
);
OutputRegister outputregister1(
.OutputRegister_out(SAP_out),
.OutputRegister_in(bus[7:0]),
.lo_(lo_),
.clk(clk),
.clr_(clr_)
);
endmodule

34
openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v Normal file
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module testSAPone;
wire [7:0] SAP_out;
wire [11:0] con;
wire [7:0] bus;
// wire clk_out, clr_out;
reg clk, clr_;
always #5 clk = ~clk;
SAPone sapone1(
.SAP_out(SAP_out),
.con(con),
.bus(bus),
// .clk_out(clk_out),
// .clr_out(clr_out),
.clk(clk),
.clr_(clr_)
);
// PC pc1(bus[3:0], clk, clr_, cp, ep);
// MAR mar1(mar, clk, lm_, bus[3:0]);
initial
begin
clk = 0; clr_ = 0;
#10 clr_ = 1;
#990 $stop;
end
endmodule

16
openfpga_flow/benchmarks/micro_benchmark/counter/counter.v Normal file
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module counter(clk_counter, q_counter, rst_counter);
input clk_counter;
input rst_counter;
output [7:0] q_counter;
reg [7:0] q_counter;
always @ (posedge clk_counter)
begin
if(rst_counter)
q_counter <= 8'b00000000;
else
q_counter <= q_counter + 1;
end
endmodule

84
openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
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@ -1,84 +0,0 @@
/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
wire _00_;
wire _01_;
input clk_counter;
wire n22;
wire n26;
wire n30;
wire n34;
wire n38;
wire n42;
wire n46;
wire n50;
output \q_counter[0] ;
reg \q_counter[0] ;
output \q_counter[1] ;
reg \q_counter[1] ;
output \q_counter[2] ;
reg \q_counter[2] ;
output \q_counter[3] ;
reg \q_counter[3] ;
output \q_counter[4] ;
reg \q_counter[4] ;
output \q_counter[5] ;
reg \q_counter[5] ;
output \q_counter[6] ;
reg \q_counter[6] ;
output \q_counter[7] ;
reg \q_counter[7] ;
input rst_counter;
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[0] <= 1'b0;
else \q_counter[0] <= n22;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[1] <= 1'b0;
else \q_counter[1] <= n26;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[2] <= 1'b0;
else \q_counter[2] <= n30;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[3] <= 1'b0;
else \q_counter[3] <= n34;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[4] <= 1'b0;
else \q_counter[4] <= n38;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[5] <= 1'b0;
else \q_counter[5] <= n42;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[6] <= 1'b0;
else \q_counter[6] <= n46;
end
always @(posedge clk_counter)
begin
if(rst_counter) \q_counter[7] <= 1'b0;
else \q_counter[7] <= n50;
end
assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] };
assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] };
assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] };
assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] };
assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] };
assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] };
assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
endmodule

69
openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
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@ -1,69 +0,0 @@
# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os)
.model counter
.inputs clk_counter rst_counter
.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7]
.names $false
.names $true
1
.names $undef
.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0]
0011 1
1000 1
1001 1
1010 1
.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_
111111 1
.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0]
010 1
100 1
.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0]
010 1
100 1
.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_
11111 1
.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0]
0011 1
1000 1
1001 1
1010 1
.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0]
001111 1
100000 1
100001 1
100010 1
100011 1
100100 1
100101 1
100110 1
100111 1
101000 1
101001 1
101010 1
101011 1
101100 1
101101 1
101110 1
.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0]
00111 1
10000 1
10001 1
10010 1
10011 1
10100 1
10101 1
10110 1
.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0]
010 1
100 1
.names q_counter[0] rst_counter $0\q_counter[0][0:0]
00 1
.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2
.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2
.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2
.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2
.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2
.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2
.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2
.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2
.end

20
openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
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@ -1,20 +0,0 @@
clk_counter 0.500000 2.000000
rst_counter 0.492200 0.201800
q_counter[0] 0.281800 0.563400
q_counter[1] 0.248200 0.273600
q_counter[2] 0.183200 0.125600
q_counter[3] 0.097400 0.044800
q_counter[4] 0.022600 0.007200
q_counter[5] 0.002200 0.000800
q_counter[6] 0.000000 0.000000
q_counter[7] 0.000000 0.000000
$0\q_counter[7][0:0] 0 0
$0\q_counter[6][0:0] 0 0
$0\q_counter[5][0:0] 0 0
$0\q_counter[4][0:0] 0 0
$0\q_counter[3][0:0] 0 0
$0\q_counter[2][0:0] 0 0
$0\q_counter[1][0:0] 0 0
$0\q_counter[0][0:0] 0 0
$abc$3686$new_n23_ 0 0
$abc$3686$new_n20_ 0 0

24
openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v Normal file
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module counter_tb;
reg clk_counter, rst_counter;
wire [7:0] q_counter;
counter_original C_1(
clk_counter,
q_counter,
rst_counter);
initial begin
#0 rst_counter = 1'b1; clk_counter = 1'b0;
#100 rst_counter = 1'b0;
end
always begin
#10 clk_counter = ~clk_counter;
end
initial begin
#5000 $stop;
end
endmodule

3
openfpga_flow/benchmarks/micro_benchmark/or2/or2.act Normal file
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@ -0,0 +1,3 @@
a 0.5 0.5
b 0.5 0.5
c 0.25 0.75

8
openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif Normal file
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@ -0,0 +1,8 @@
.model or2
.inputs a b
.outputs c
.names a b c
00 0
.end

18
openfpga_flow/benchmarks/micro_benchmark/or2/or2.v Normal file
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@ -0,0 +1,18 @@
/////////////////////////////////////////
// Functionality: 2-input OR
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module or2(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a | b;
endmodule

24
openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml
View File

@ -1,35 +1,35 @@
<fabric_key>
<key id="0" name="sb_2__2_" value="0" alias="sb_2__2_"/>
<key id="1" name="grid_clb" value="3" alias="grid_clb_2_2"/>
<key id="1" name="grid_clb" value="3" alias="grid_clb_2__2_"/>
<key id="2" name="sb_0__1_" value="0" alias="sb_0__1_"/>
<key id="3" name="cby_0__1_" value="0" alias="cby_0__1_"/>
<key id="4" name="grid_clb" value="2" alias="grid_clb_2_1"/>
<key id="5" name="grid_io_left" value="0" alias="grid_io_left_0_1"/>
<key id="4" name="grid_clb" value="2" alias="grid_clb_2__1_"/>
<key id="5" name="grid_io_left" value="0" alias="grid_io_left_0__1_"/>
<key id="6" name="sb_1__0_" value="0" alias="sb_1__0_"/>
<key id="7" name="sb_1__1_" value="0" alias="sb_1__1_"/>
<key id="8" name="cbx_1__1_" value="1" alias="cbx_2__1_"/>
<key id="9" name="cby_1__1_" value="1" alias="cby_1__2_"/>
<key id="10" name="grid_io_right" value="1" alias="grid_io_right_3_2"/>
<key id="10" name="grid_io_right" value="1" alias="grid_io_right_3__2_"/>
<key id="11" name="cbx_1__0_" value="1" alias="cbx_2__0_"/>
<key id="12" name="cby_1__1_" value="0" alias="cby_1__1_"/>
<key id="13" name="grid_io_right" value="0" alias="grid_io_right_3_1"/>
<key id="14" name="grid_io_bottom" value="0" alias="grid_io_bottom_1_0"/>
<key id="13" name="grid_io_right" value="0" alias="grid_io_right_3__1_"/>
<key id="14" name="grid_io_bottom" value="0" alias="grid_io_bottom_1__0_"/>
<key id="15" name="cby_2__1_" value="0" alias="cby_2__1_"/>
<key id="16" name="sb_2__1_" value="0" alias="sb_2__1_"/>
<key id="17" name="cbx_1__0_" value="0" alias="cbx_1__0_"/>
<key id="18" name="grid_clb" value="1" alias="grid_clb_1_2"/>
<key id="18" name="grid_clb" value="1" alias="grid_clb_1__2_"/>
<key id="19" name="cbx_1__2_" value="0" alias="cbx_1__2_"/>
<key id="20" name="cbx_1__2_" value="1" alias="cbx_2__2_"/>
<key id="21" name="sb_2__0_" value="0" alias="sb_2__0_"/>
<key id="22" name="sb_1__2_" value="0" alias="sb_1__2_"/>
<key id="23" name="cby_0__1_" value="1" alias="cby_0__2_"/>
<key id="24" name="sb_0__0_" value="0" alias="sb_0__0_"/>
<key id="25" name="grid_clb" value="0" alias="grid_clb_1_1"/>
<key id="25" name="grid_clb" value="0" alias="grid_clb_1__1_"/>
<key id="26" name="cby_2__1_" value="1" alias="cby_2__2_"/>
<key id="27" name="grid_io_top" value="1" alias="grid_io_top_2_3"/>
<key id="27" name="grid_io_top" value="1" alias="grid_io_top_2__3_"/>
<key id="28" name="sb_0__2_" value="0" alias="sb_0__2_"/>
<key id="29" name="grid_io_bottom" value="1" alias="grid_io_bottom_2_0"/>
<key id="29" name="grid_io_bottom" value="1" alias="grid_io_bottom_2__0_"/>
<key id="30" name="cbx_1__1_" value="0" alias="cbx_1__1_"/>
<key id="31" name="grid_io_top" value="0" alias="grid_io_top_1_3"/>
<key id="32" name="grid_io_left" value="1" alias="grid_io_left_0_2"/>
<key id="31" name="grid_io_top" value="0" alias="grid_io_top_1__3_"/>
<key id="32" name="grid_io_left" value="1" alias="grid_io_left_0__2_"/>
</fabric_key>

1
openfpga_flow/openfpga_arch/README.md
View File

@ -23,5 +23,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
- stdcell: If circuit designs are built with standard cells only
- tree\_mux: If routing multiplexers are built with a tree-like structure
- <feature_size>: The technology node which the delay numbers are extracted from.
- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
Other features are used in naming should be listed here.

206
openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml Normal file
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@ -0,0 +1,206 @@
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<!-- An inverter with a pair of power-gate control signals
en port: when it is '1', it is power gated
enb port: when it is '0', it is power gated
-->
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" power_gated="true" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="en" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="enb" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

6
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -242,7 +242,7 @@
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
@ -277,7 +277,7 @@
<pb_type name="clb_spypad.fle" physical_mode_name="physical"/>
<!-- Binding regular FLEs -->
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
@ -310,7 +310,7 @@
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="11"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/>
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->

231
openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml Normal file
View File

@ -0,0 +1,231 @@
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N8_40nm.xml
- General purpose logic block
- K = 6, N = 8, I = 32
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="64"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:4]"/>
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:5]"/>
<port name="out" physical_mode_port="lut6_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

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<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml
- General purpose logic block
- K = 6, N = 8, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true" local_encoder="true">
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="64"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:4]"/>
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:5]"/>
<port name="out" physical_mode_port="lut6_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

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<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml
- General purpose logic block
- K = 6, N = 8, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<!-- Define a circuit model for the standard cell MUX2
OpenFPGA requires the following truth table for the MUX2
When the select signal sel is enabled, the first input, i.e., in0
will be propagated to the output, i.e., out
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
<circuit_model type="gate" name="MUX2" prefix="MUX2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mux2.v">
<design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in0" lib_name="B" size="1"/>
<port type="input" prefix="in1" lib_name="A" size="1"/>
<port type="input" prefix="sel" lib_name="S0" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
<pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="64"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:4]"/>
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:5]"/>
<port name="out" physical_mode_port="lut6_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

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<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml
- General purpose logic block
- K = 6, N = 8, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="MUX2" prefix="MUX2" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
<pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="64"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:4]"/>
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:5]"/>
<port name="out" physical_mode_port="lut6_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

5
openfpga_flow/tasks/behavioral_verilog/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml

5
openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml

5
openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml

5
openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/iverilog_example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/iverilog_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml

5
openfpga_flow/tasks/bram/dpram16k/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml

5
openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml

5
openfpga_flow/tasks/compilation_verification/config/task.conf
View File

@ -8,16 +8,17 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

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