diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 6c9e1c04d..b794858d9 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -36,7 +36,7 @@ echo -e "Testing Verilog testbench generation only"; python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs echo -e "Testing bitstream generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py generate_bitstream --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs @@ -44,4 +44,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug echo -e "Testing SDC generation with time units"; python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs +echo -e "Testing FPGA-SPICE with netlist generation"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs + end_section "OpenFPGA.TaskTun" diff --git a/.travis/verilog_reg_test.sh b/.travis/verilog_reg_test.sh index f49b6ab84..18ffe91e5 100755 --- a/.travis/verilog_reg_test.sh +++ b/.travis/verilog_reg_test.sh @@ -75,6 +75,12 @@ python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_vanilla_key - python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_random_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/load_external_key --debug --show_thread_logs +echo -e "Testing Power-gating designs"; +python3 openfpga_flow/scripts/run_fpga_task.py power_gated_design/power_gated_inverter --show_thread_logs --debug + +echo -e "Testing Depopulated crossbar in local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py depopulate_crossbar --debug --show_thread_logs + # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail diff --git a/docs/source/manual/arch_lang/technology_library.rst b/docs/source/manual/arch_lang/technology_library.rst index 08b6c62d9..4d1c5f2a0 100644 --- a/docs/source/manual/arch_lang/technology_library.rst +++ b/docs/source/manual/arch_lang/technology_library.rst @@ -13,8 +13,8 @@ General organization is as follows. - - + + @@ -71,15 +71,19 @@ A device model represents a transistor/RRAM model available in users' technology - ``pn_ratio=""`` specify the ratio between *p*-type and *n*-type transistors. The ratio will be used when building circuit structures such as inverters, buffers, etc. -.. option:: +.. option:: Specify device-level parameters for transistors - ``name=""`` specify the name of the p/n type transistor, which can be found in the manual of the technology provider. - - ``chan_length=""`` specify the channel length of *p/n* type transistor. + - ``chan_length=""`` specify the channel length of a *p/n* type transistor. - - ``min_width=""`` specify the minimum width of *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing. + - ``min_width=""`` specify the minimum width of a *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing. + + - ``max_width=""`` specify the maximum width of a *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing. If the required transistor width exceeds the maximum width, multiple transistors will be instanciated. Note that for FinFET technology, your ``max_width`` should be the same as your ``min_width``. + + .. note:: The ``max_width`` is optional. By default, it will be set to be same as the ``min_width``. - ``variation=""`` specify the variation name defined in the ```` diff --git a/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst b/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst index 280768c1a..131d0ce57 100644 --- a/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst +++ b/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst @@ -1,7 +1,133 @@ Fabric-dependent Bitstream ~~~~~~~~~~~~~~~~~~~~~~~~~~ +Usage +````` + Fabric-dependent bitstream is design to be loadable to the configuration protocols of FPGAs. The bitstream just sets an order to the configuration bits in the database, without duplicating the database. OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists. -The fabric-dependent bitstream can be found in autogenerated Verilog testbenches. +The fabric-dependent bitstream can be found in the pre-configured Verilog testbenches. +The fabric bitsteam can be outputted in different file format in terms of usage. + +Plain Text File Format +``````````````````````` + +This file format is designed to be directly loaded to an FPGA fabric. +It does not include any comments but only bitstream. + +The information depends on the type of configuration procotol. + +.. option:: vanilla + + A line consisting of ``0`` | ``1`` + +.. option:: scan_chain + + A line consisting of ``0`` | ``1`` + +.. option:: memory_bank + + Multiple lines will be included, each of which is organized as
. + Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired. + The first line represents the Bit-Line address and configuration bit. + The second line represents the Word-Line address and configuration bit. + For example + + .. code-block:: xml + + + + + + ... + + + +.. option:: frame_based + + Multiple lines will be included, each of which is organized as
. + For example + + .. code-block:: xml + + + + ... + + +XML File Format +``````````````` + +This file format is designed to generate testbenches using external tools, e.g., CocoTB. + +In principle, the file consist a number of XML node ````, each bit contains the following attributes: + +- ``id``: The unique id of the configuration bit in the fabric bitstream. + +- ``value``: The configuration bit value. + + - ``hierarchy`` represents the location of this block in FPGA fabric. + The hierachy includes the full hierarchy of this block + + - ``instance`` denotes the instance name which you can find in the fabric netlists + + - ``level`` denotes the depth of the block in the hierarchy + + - ``width`` denotes the number of configuration bits under the instance. Typically, only leaf instance has this attribute. + +A quick example: + +.. code-block:: xml + + + + + + + + + + +Other information may depend on the type of configuration procotol. + +.. option:: memory_bank + + - ``bl``: Bit line address information + + - ``wl``: Word line address information + + A quick example: + + .. code-block:: xml + + + + + + + + + + + + + +.. option:: frame_based + + - ``frame``: frame address information + + A quick example: + + .. code-block:: xml + + + + + + + + + + + diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst index 731f99f94..5c1bf5d2b 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst @@ -7,8 +7,8 @@ repack ~~~~~~ Repack the netlist to physical pbs - This must be done before bitstream generator and testbench generation - Strongly recommend it is done after all the fix-up have been applied + + .. note:: This must be done before bitstream generator and testbench generation. Strongly recommend it is done after all the fix-up have been applied - ``--verbose`` Show verbose log @@ -28,6 +28,15 @@ build_fabric_bitstream Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric + - ``--verbose`` Show verbose log + +write_fabric_bitstream +~~~~~~~~~~~~~~~~~~~~~~ + + Output the fabric bitstream database to a specific file format + - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1) + - ``--format`` Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``. + - ``--verbose`` Show verbose log diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index de4aecad8..c2044cf57 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -31,7 +31,7 @@ write_verilog_testbench - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches - - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index aa0018476..2d628117a 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -109,6 +109,10 @@ build_fabric - ``--write_fabric_key `` Output current fabric key to an XML file + - ``--frame_view`` Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory. + + .. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists! + - ``--verbose`` Show verbose log .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp index b38fbf1b6..ea6db0678 100644 --- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp @@ -302,7 +302,9 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, return num_err; } -/* Check all the ports make sure, they satisfy the restriction */ +/************************************************************************ + * Check all the ports make sure, they satisfy the restriction + ***********************************************************************/ static size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { size_t num_err = 0; @@ -435,6 +437,94 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { return num_err; } +/************************************************************************ + * Check the port requirements for a power-gated circuit model + * - It must have at least 2 global ports and which are config enable signals + * - It must have an Enable port which control power gating + * - It must have an EnableB port which control power gating + ***********************************************************************/ +static +int check_power_gated_circuit_model(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + int num_err = 0; + + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true); + + /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ + VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model)); + /* Check all the ports we have are good for a power-gated circuit model */ + /* We need at least one global port */ + if (2 > global_ports.size()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Expect at least two global ports (a pair of EN/Enb) for circuit model '%s' which is power-gated!\n", + circuit_lib.model_name(circuit_model).c_str()); + num_err++; + } + /* All the global ports should be config_enable */ + int num_config_enable_ports = 0; + for (const auto& port : global_ports) { + if (true == circuit_lib.port_is_config_enable(port)) { + num_config_enable_ports++; + } + } + + if (2 != num_config_enable_ports) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Circuit model '%s' is power-gated. Two config-enable global ports are required!\n", + circuit_lib.model_name(circuit_model).c_str()); + num_err++; + } + /* Report errors if there are any */ + if (0 < num_err) { + return num_err; + } + + /* Try to find a pair of Enable and ENb ports from the global ports */ + CircuitPortId en_port = CircuitPortId::INVALID(); + CircuitPortId enb_port = CircuitPortId::INVALID(); + for (const auto& port : global_ports) { + /* Focus on config_enable ports which are power-gate control signals */ + if (false == circuit_lib.port_is_config_enable(port)) { + continue; + } + if (0 == circuit_lib.port_default_value(port)) { + en_port = port; + } else { + VTR_ASSERT(1 == circuit_lib.port_default_value(port)); + enb_port = port; + } + } + /* We must have valid EN/ENb ports */ + if (false == circuit_lib.valid_circuit_port_id(en_port)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Fail to find an enable port for the circuit model '%s' is power-gated!\n", + circuit_lib.model_name(circuit_model).c_str()); + } + if (false == circuit_lib.valid_circuit_port_id(enb_port)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Fail to find an inverted enable port for the circuit model '%s' is power-gated!\n", + circuit_lib.model_name(circuit_model).c_str()); + } + + return num_err; +} + +/************************************************************************ + * Check the port requirements for each power-gated circuit model + ***********************************************************************/ +static +int check_power_gated_circuit_models(const CircuitLibrary& circuit_lib) { + int num_err = 0; + + for (const CircuitModelId& circuit_model : circuit_lib.models()) { + if (true == circuit_lib.is_power_gated(circuit_model)) { + num_err += check_power_gated_circuit_model(circuit_lib, circuit_model); + } + } + + return num_err; +} + /************************************************************************ * Check points to make sure we have a valid circuit library * Detailed checkpoints: @@ -541,6 +631,9 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_CHAN_WIRE); num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_WIRE); + /* 11. Check power-gated inverter/buffer models */ + num_err += check_power_gated_circuit_models(circuit_lib); + /* If we have any errors, exit */ if (0 < num_err) { diff --git a/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp index f2f082116..e2871a638 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp @@ -122,6 +122,14 @@ void read_xml_device_transistor(pugi::xml_node& xml_device_transistor, tech_lib.set_transistor_model_min_width(device_model, transistor_type, get_attribute(xml_device_transistor, "min_width", loc_data).as_float(0.)); + /* Parse the transistor maximum width, by default we consider the same as minimum width */ + tech_lib.set_transistor_model_max_width(device_model, transistor_type, + get_attribute(xml_device_transistor, "max_width", loc_data, pugiutil::ReqOpt::OPTIONAL).as_float(0.)); + /* If the max_width is default value, we set it to be the same as min_width */ + if (0. == tech_lib.transistor_model_max_width(device_model, transistor_type)) { + tech_lib.set_transistor_model_max_width(device_model, transistor_type, tech_lib.transistor_model_min_width(device_model, transistor_type)); + } + /* Parse the transistor variation name */ tech_lib.set_transistor_model_variation_name(device_model, transistor_type, get_attribute(xml_device_transistor, "variation", loc_data).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/technology_library.cpp b/libopenfpga/libarchopenfpga/src/technology_library.cpp index 3f8e8e7f9..aa97abe80 100644 --- a/libopenfpga/libarchopenfpga/src/technology_library.cpp +++ b/libopenfpga/libarchopenfpga/src/technology_library.cpp @@ -157,6 +157,18 @@ float TechnologyLibrary::transistor_model_min_width(const TechnologyModelId& mod return transistor_model_min_widths_[model_id][transistor_type]; } +/* Access the maximum width of a transistor (either PMOS or NMOS) for a technology model + * Note: This is ONLY applicable to transistor model + */ +float TechnologyLibrary::transistor_model_max_width(const TechnologyModelId& model_id, + const e_tech_lib_transistor_type& transistor_type) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* This is only applicable to transistor model */ + VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == model_type(model_id)); + return transistor_model_max_widths_[model_id][transistor_type]; +} + /* Access the minimum width of a transistor (either PMOS or NMOS) for a technology model * Note: This is ONLY applicable to transistor model */ @@ -270,6 +282,7 @@ TechnologyModelId TechnologyLibrary::add_model(const std::string& name) { transistor_model_names_.emplace_back(); transistor_model_chan_lengths_.emplace_back(); transistor_model_min_widths_.emplace_back(); + transistor_model_max_widths_.emplace_back(); transistor_model_variation_names_.emplace_back(); transistor_model_variation_ids_.push_back(std::array{TechnologyVariationId::INVALID(), TechnologyVariationId::INVALID()}); @@ -394,6 +407,19 @@ void TechnologyLibrary::set_transistor_model_min_width(const TechnologyModelId& return; } +/* Set the maximum width for either PMOS or NMOS of a model in the library + * This is ONLY applicable to transistors + */ +void TechnologyLibrary::set_transistor_model_max_width(const TechnologyModelId& model_id, + const e_tech_lib_transistor_type& transistor_type, + const float& max_width) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == model_type(model_id)); + transistor_model_max_widths_[model_id][transistor_type] = max_width; + return; +} + /* Set the variation name for either PMOS or NMOS of a model in the library * This is ONLY applicable to transistors */ diff --git a/libopenfpga/libarchopenfpga/src/technology_library.h b/libopenfpga/libarchopenfpga/src/technology_library.h index a38acade3..ba90eff1d 100644 --- a/libopenfpga/libarchopenfpga/src/technology_library.h +++ b/libopenfpga/libarchopenfpga/src/technology_library.h @@ -101,6 +101,8 @@ class TechnologyLibrary { const e_tech_lib_transistor_type& transistor_type) const; float transistor_model_min_width(const TechnologyModelId& model_id, const e_tech_lib_transistor_type& transistor_type) const; + float transistor_model_max_width(const TechnologyModelId& model_id, + const e_tech_lib_transistor_type& transistor_type) const; TechnologyVariationId transistor_model_variation(const TechnologyModelId& model_id, const e_tech_lib_transistor_type& transistor_type) const; public: /* Public Accessors: Basic data query on RRAM models */ @@ -138,6 +140,9 @@ class TechnologyLibrary { void set_transistor_model_min_width(const TechnologyModelId& model_id, const e_tech_lib_transistor_type& transistor_type, const float& min_width); + void set_transistor_model_max_width(const TechnologyModelId& model_id, + const e_tech_lib_transistor_type& transistor_type, + const float& max_width); void set_transistor_model_variation_name(const TechnologyModelId& model_id, const e_tech_lib_transistor_type& transistor_type, const std::string& variation_name); @@ -231,6 +236,15 @@ class TechnologyLibrary { */ vtr::vector> transistor_model_min_widths_; + /* The maximum width of a transistor. + * This should be defined by your technology vendor + * The maximum width of a transistor will be used to size your transistors + * If the required width in circuit models in larger then the max width, + * multiple transistor bin will be instanciated. + * For FinFET, the maximum width should be the same as min_width + */ + vtr::vector> transistor_model_max_widths_; + /* The variation name and id binded to PMOS and NMOS transistor * We expect users to provide the exact name of variation defined in this technology library * the name and id will be automatically matched by using function link_model_to_variation() diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index 88fc0d3b2..5dd69ca8e 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -92,6 +92,25 @@ void write_xml_design_technology(std::fstream& fp, fp << "/>" << "\n"; } +/******************************************************************** + * A writer to output the device technology of a circuit model to XML format + *******************************************************************/ +static +void write_xml_device_technology(std::fstream& fp, + const char* fname, + const CircuitLibrary& circuit_lib, + const CircuitModelId& model) { + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + if (!circuit_lib.device_model_name(model).empty()) { + fp << "\t\t\t" << "" << "\n"; + } +} + /******************************************************************** * A writer to output a circuit port to XML format *******************************************************************/ @@ -401,6 +420,9 @@ void write_xml_circuit_model(std::fstream& fp, /* Write the design technology of circuit model */ write_xml_design_technology(fp, fname, circuit_lib, model); + /* Write the device technology of circuit model */ + write_xml_device_technology(fp, fname, circuit_lib, model); + /* Write the input buffer information of circuit model, * only applicable when this circuit model is neither inverter nor buffer */ diff --git a/libopenfpga/libarchopenfpga/src/write_xml_technology_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_technology_library.cpp index 6f3f6fe0d..bf15bbe32 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_technology_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_technology_library.cpp @@ -60,6 +60,7 @@ void write_xml_device_model(std::fstream& fp, write_xml_attribute(fp, "name", tech_lib.transistor_model_name(device_model, TECH_LIB_TRANSISTOR_PMOS).c_str()); write_xml_attribute(fp, "chan_length", tech_lib.transistor_model_chan_length(device_model, TECH_LIB_TRANSISTOR_PMOS)); write_xml_attribute(fp, "min_width", tech_lib.transistor_model_min_width(device_model, TECH_LIB_TRANSISTOR_PMOS)); + write_xml_attribute(fp, "max_width", tech_lib.transistor_model_max_width(device_model, TECH_LIB_TRANSISTOR_PMOS)); if (TechnologyVariationId::INVALID() != tech_lib.transistor_model_variation(device_model, TECH_LIB_TRANSISTOR_PMOS)) { write_xml_attribute(fp, "variation", tech_lib.variation_name(tech_lib.transistor_model_variation(device_model, TECH_LIB_TRANSISTOR_PMOS)).c_str()); } diff --git a/libopenfpga/libfpgabitstream/src/bitstream_manager.cpp b/libopenfpga/libfpgabitstream/src/bitstream_manager.cpp index eb62222fb..3d5052989 100644 --- a/libopenfpga/libfpgabitstream/src/bitstream_manager.cpp +++ b/libopenfpga/libfpgabitstream/src/bitstream_manager.cpp @@ -52,6 +52,13 @@ bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const { return '1' == bit_values_[bit_id]; } +ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) const { + /* Ensure a valid id */ + VTR_ASSERT(true == valid_bit_id(bit_id)); + + return bit_parent_blocks_[bit_id]; +} + std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block_id)); @@ -140,7 +147,7 @@ std::string BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id /****************************************************************************** * Public Mutators ******************************************************************************/ -ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { +ConfigBitId BitstreamManager::add_bit(const ConfigBlockId& parent_block, const bool& bit_value) { ConfigBitId bit = ConfigBitId(num_bits_); /* Add a new bit, and allocate associated data structures */ num_bits_++; @@ -150,6 +157,8 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { bit_values_.push_back('0'); } + bit_parent_blocks_.push_back(parent_block); + return bit; } @@ -234,7 +243,7 @@ void BitstreamManager::add_block_bits(const ConfigBlockId& block, block_bit_id_lsbs_[block] = num_bits_; block_bit_lengths_[block] = block_bitstream.size(); for (const bool& bit : block_bitstream) { - add_bit(bit); + add_bit(block, bit); } } diff --git a/libopenfpga/libfpgabitstream/src/bitstream_manager.h b/libopenfpga/libfpgabitstream/src/bitstream_manager.h index 84c3ec97c..32575c5db 100644 --- a/libopenfpga/libfpgabitstream/src/bitstream_manager.h +++ b/libopenfpga/libfpgabitstream/src/bitstream_manager.h @@ -119,6 +119,9 @@ class BitstreamManager { /* Find the value of bitstream */ bool bit_value(const ConfigBitId& bit_id) const; + /* Find the parent block of a configuration bit */ + ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const; + /* Find a name of a block */ std::string block_name(const ConfigBlockId& block_id) const; @@ -145,7 +148,7 @@ class BitstreamManager { public: /* Public Mutators */ /* Add a new configuration bit to the bitstream manager */ - ConfigBitId add_bit(const bool& bit_value); + ConfigBitId add_bit(const ConfigBlockId& parent_block, const bool& bit_value); /* Reserve memory for a number of clocks */ void reserve_blocks(const size_t& num_blocks); @@ -235,6 +238,7 @@ class BitstreamManager { std::unordered_set invalid_bit_ids_; /* value of a bit in the Bitstream */ vtr::vector bit_values_; + vtr::vector bit_parent_blocks_; }; } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index 3fbffc45d..138ee2032 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -16,7 +16,8 @@ #include "write_xml_arch_bitstream.h" #include "build_device_bitstream.h" -#include "fabric_bitstream_writer.h" +#include "write_text_fabric_bitstream.h" +#include "write_xml_fabric_bitstream.h" #include "build_fabric_bitstream.h" #include "openfpga_bitstream.h" @@ -65,7 +66,6 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); - CommandOptionId opt_file = cmd.option("file"); /* Build fabric bitstream here */ openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(), @@ -73,21 +73,51 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, openfpga_ctx.arch().config_protocol, cmd_context.option_enable(cmd, opt_verbose)); + /* TODO: should identify the error code from internal function execution */ + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * A wrapper function to call the write_fabric_bitstream() in FPGA bitstream + *******************************************************************/ +int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { + + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_file_format = cmd.option("format"); + /* Write fabric bitstream if required */ int status = CMD_EXEC_SUCCESS; - if (true == cmd_context.option_enable(cmd, opt_file)) { - std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file)); + + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); - /* Create directories */ - create_directory(src_dir_path); + std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file)); + /* Create directories */ + create_directory(src_dir_path); + + /* Check file format requirements */ + std::string file_format("plain_text"); + if (true == cmd_context.option_enable(cmd, opt_file_format)) { + file_format = cmd_context.option_value(cmd, opt_file_format); + } + + if (std::string("xml") == file_format) { + status = write_fabric_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(), + openfpga_ctx.fabric_bitstream(), + openfpga_ctx.arch().config_protocol, + cmd_context.option_value(cmd, opt_file), + cmd_context.option_enable(cmd, opt_verbose)); + } else { + /* By default, output in plain text format */ status = write_fabric_bitstream_to_text_file(openfpga_ctx.bitstream_manager(), openfpga_ctx.fabric_bitstream(), openfpga_ctx.arch().config_protocol, - cmd_context.option_value(cmd, opt_file)); + cmd_context.option_value(cmd, opt_file), + cmd_context.option_enable(cmd, opt_verbose)); } - /* TODO: should identify the error code from internal function execution */ return status; } diff --git a/openfpga/src/base/openfpga_bitstream.h b/openfpga/src/base/openfpga_bitstream.h index 58f1c7e86..c210d6bab 100644 --- a/openfpga/src/base/openfpga_bitstream.h +++ b/openfpga/src/base/openfpga_bitstream.h @@ -21,6 +21,9 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx, int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context); +int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index 1a337e9d0..fef8dca89 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -41,9 +41,9 @@ ShellCommandId add_openfpga_repack_command(openfpga::Shell& she * - Add command dependency *******************************************************************/ static -ShellCommandId add_openfpga_arch_bitstream_command(openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { +ShellCommandId add_openfpga_build_arch_bitstream_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { Command shell_cmd("build_architecture_bitstream"); /* Add an option '--write_file' */ @@ -75,16 +75,11 @@ ShellCommandId add_openfpga_arch_bitstream_command(openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { +ShellCommandId add_openfpga_build_fabric_bitstream_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { Command shell_cmd("build_fabric_bitstream"); - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option("file", false, "file path to output the fabric bitstream to plain text file"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Enable verbose output"); @@ -99,6 +94,40 @@ ShellCommandId add_openfpga_fabric_bitstream_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_fabric_bitstream"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to output the fabric bitstream to plain text file"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--file_format'*/ + CommandOptionId opt_file_format = shell_cmd.add_option("format", false, "file format of fabric bitstream [plain_text|xml]. Default: plain_text"); + shell_cmd.set_option_require_value(opt_file_format, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'fabric_bitstream' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Write the fabric-dependent bitstream to a file"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_fabric_bitstream); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + /******************************************************************** * Top-level function to add all the commands related to FPGA-Bitstream *******************************************************************/ @@ -121,17 +150,25 @@ void add_openfpga_bitstream_commands(openfpga::Shell& shell) { * Command 'build_architecture_bitstream' */ /* The 'build_architecture_bitstream' command should NOT be executed before 'repack' */ - std::vector cmd_dependency_arch_bitstream; - cmd_dependency_arch_bitstream.push_back(shell_cmd_repack_id); - ShellCommandId shell_cmd_arch_bitstream_id = add_openfpga_arch_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_arch_bitstream); + std::vector cmd_dependency_build_arch_bitstream; + cmd_dependency_build_arch_bitstream.push_back(shell_cmd_repack_id); + ShellCommandId shell_cmd_build_arch_bitstream_id = add_openfpga_build_arch_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_build_arch_bitstream); /******************************** * Command 'build_fabric_bitstream' */ /* The 'build_fabric_bitstream' command should NOT be executed before 'build_architecture_bitstream' */ - std::vector cmd_dependency_fabric_bitstream; - cmd_dependency_fabric_bitstream.push_back(shell_cmd_arch_bitstream_id); - add_openfpga_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_fabric_bitstream); + std::vector cmd_dependency_build_fabric_bitstream; + cmd_dependency_build_fabric_bitstream.push_back(shell_cmd_build_arch_bitstream_id); + ShellCommandId shell_cmd_build_fabric_bitstream_id = add_openfpga_build_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_build_fabric_bitstream); + + /******************************** + * Command 'write_fabric_bitstream' + */ + /* The 'write_fabric_bitstream' command should NOT be executed before 'build_fabric_bitstream' */ + std::vector cmd_dependency_write_fabric_bitstream; + cmd_dependency_write_fabric_bitstream.push_back(shell_cmd_build_fabric_bitstream_id); + add_openfpga_write_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_write_fabric_bitstream); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index f4a72ff61..f743ef3f6 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -238,7 +238,7 @@ std::string generate_routing_block_netlist_name(const std::string& prefix, std::string generate_routing_block_netlist_name(const std::string& prefix, const vtr::Point& coordinate, const std::string& postfix) { - return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix ); + return std::string( prefix + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") + postfix ); } /********************************************************************* @@ -968,10 +968,8 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, std::string generate_logical_tile_netlist_name(const std::string& prefix, const t_pb_graph_node* pb_graph_head, const std::string& postfix) { - /* This must be the root node */ - VTR_ASSERT(true == pb_graph_head->is_root()); /* Add the name of physical block */ - std::string module_name = prefix + std::string(pb_graph_head->pb_type->name); + std::string module_name = prefix + generate_physical_block_module_name(pb_graph_head->pb_type); module_name += postfix; @@ -1183,8 +1181,9 @@ std::string generate_grid_block_instance_name(const std::string& prefix, module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string()); module_name += std::string("_"); module_name += std::to_string(grid_coord.x()); - module_name += std::string("_"); + module_name += std::string("__"); module_name += std::to_string(grid_coord.y()); + module_name += std::string("_"); return module_name; } @@ -1244,7 +1243,6 @@ std::string generate_physical_block_module_name(t_pb_type* physical_pb_type) { return module_name; } - /********************************************************************* * Generate the instance name for physical block with a given index **********************************************************************/ diff --git a/openfpga/src/base/openfpga_spice.cpp b/openfpga/src/base/openfpga_spice.cpp index 2b99d33e8..4ef4058ee 100644 --- a/openfpga/src/base/openfpga_spice.cpp +++ b/openfpga/src/base/openfpga_spice.cpp @@ -39,7 +39,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx, int status = CMD_EXEC_SUCCESS; status = fpga_fabric_spice(openfpga_ctx.module_graph(), openfpga_ctx.mutable_spice_netlists(), - openfpga_ctx.arch().tech_lib, + openfpga_ctx.arch(), options); return status; diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp similarity index 93% rename from openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp rename to openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp index 2991dd6a0..f96747212 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp +++ b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp @@ -1,6 +1,6 @@ /******************************************************************** * This file includes functions that output a fabric-dependent - * bitstream database to files in different formats + * bitstream database to files in plain text *******************************************************************/ #include #include @@ -17,7 +17,7 @@ #include "openfpga_naming.h" #include "bitstream_manager_utils.h" -#include "fabric_bitstream_writer.h" +#include "write_text_fabric_bitstream.h" /* begin namespace openfpga */ namespace openfpga { @@ -95,7 +95,8 @@ int write_fabric_config_bit_to_text_file(std::fstream& fp, int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const ConfigProtocol& config_protocol, - const std::string& fname) { + const std::string& fname, + const bool& verbose) { /* Ensure that we have a valid file name */ if (true == fname.empty()) { VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n"); @@ -127,6 +128,11 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage /* Close file handler */ fp.close(); + VTR_LOGV(verbose, + "Outputted %lu configuration bits to plain text file: %s\n", + fabric_bitstream.bits().size(), + fname.c_str()); + return status; } diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h similarity index 86% rename from openfpga/src/fpga_bitstream/fabric_bitstream_writer.h rename to openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h index bcf5466b7..9582a185c 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h +++ b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h @@ -1,5 +1,5 @@ -#ifndef FABRIC_BITSTREAM_WRITER_H -#define FABRIC_BITSTREAM_WRITER_H +#ifndef WRITE_TEXT_FABRIC_BITSTREAM_H +#define WRITE_TEXT_FABRIC_BITSTREAM_H /******************************************************************** * Include header files that are required by function declaration @@ -20,7 +20,8 @@ namespace openfpga { int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const ConfigProtocol& config_protocol, - const std::string& fname); + const std::string& fname, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp new file mode 100644 index 000000000..b1d5aeebe --- /dev/null +++ b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp @@ -0,0 +1,208 @@ +/******************************************************************** + * This file includes functions that output a fabric-dependent + * bitstream database to files in XML format + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" + +/* Headers from archopenfpga library */ + +#include "openfpga_naming.h" + +#include "bitstream_manager_utils.h" +#include "write_xml_fabric_bitstream.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This function write header information to a bitstream file + *******************************************************************/ +static +void write_fabric_bitstream_xml_file_head(std::fstream& fp) { + valid_file_stream(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << "" << std::endl; + fp << std::endl; +} + +/******************************************************************** + * Write a configuration bit into a plain text file + * General format + * + * + * + * + * + * ... + * + * The format depends on the type of configuration protocol + * - Vanilla (standalone): No more information to be included + * - Configuration chain: No more information to be included + * - Memory bank : + * + * + * - Frame-based configuration protocol : + * + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +static +int write_fabric_config_bit_to_xml_file(std::fstream& fp, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream, + const FabricBitId& fabric_bit, + const e_config_protocol_type& config_type) { + if (false == valid_file_stream(fp)) { + return 1; + } + + write_tab_to_file(fp, 1); + fp << "\n"; + + /* Output hierarchy of this parent*/ + const ConfigBitId& config_bit = fabric_bitstream.config_bit(fabric_bit); + const ConfigBlockId& config_block = bitstream_manager.bit_parent_block(config_bit); + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block); + write_tab_to_file(fp, 2); + fp << "\n"; + size_t hierarchy_counter = 0; + for (const ConfigBlockId& temp_block : block_hierarchy) { + write_tab_to_file(fp, 3); + fp << "\n"; + hierarchy_counter++; + } + write_tab_to_file(fp, 2); + fp << "\n"; + + switch (config_type) { + case CONFIG_MEM_STANDALONE: + case CONFIG_MEM_SCAN_CHAIN: + break; + case CONFIG_MEM_MEMORY_BANK: { + /* Bit line address */ + write_tab_to_file(fp, 2); + fp << "\n"; + + write_tab_to_file(fp, 2); + fp << "\n"; + break; + } + case CONFIG_MEM_FRAME_BASED: { + write_tab_to_file(fp, 2); + fp << "\n"; + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid configuration protocol type!\n"); + return 1; + } + + write_tab_to_file(fp, 1); + fp << "\n"; + + return 0; +} + +/******************************************************************** + * Write the fabric bitstream to an XML file + * Notes: + * - This file is designed to be reused by testbench generators, e.g., CocoTB + * - It can NOT be directly loaded to the FPGA fabric + * - It include configurable memory paths in full hierarchy + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream, + const ConfigProtocol& config_protocol, + const std::string& fname, + const bool& verbose) { + /* Ensure that we have a valid file name */ + if (true == fname.empty()) { + VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n"); + } + + std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.num_bits()) + std::string(" fabric bitstream into xml file '") + fname + std::string("'"); + vtr::ScopedStartFinishTimer timer(timer_message); + + /* Create the file stream */ + std::fstream fp; + fp.open(fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(fname.c_str(), fp); + + /* Write XML head */ + write_fabric_bitstream_xml_file_head(fp); + + fp << "\n"; + + /* Output fabric bitstream to the file */ + int status = 0; + for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) { + status = write_fabric_config_bit_to_xml_file(fp, bitstream_manager, + fabric_bitstream, + fabric_bit, + config_protocol.type()); + if (1 == status) { + break; + } + } + + /* Print an end to the file here */ + fp << "\n"; + + /* Close file handler */ + fp.close(); + + VTR_LOGV(verbose, + "Outputted %lu configuration bits to XML file: %s\n", + fabric_bitstream.bits().size(), + fname.c_str()); + + return status; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.h b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.h new file mode 100644 index 000000000..73bf57912 --- /dev/null +++ b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.h @@ -0,0 +1,28 @@ +#ifndef WRITE_XML_FABRIC_BITSTREAM_H +#define WRITE_XML_FABRIC_BITSTREAM_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include +#include "bitstream_manager.h" +#include "fabric_bitstream.h" +#include "config_protocol.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream, + const ConfigProtocol& config_protocol, + const std::string& fname, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp index ab65794ac..658d43851 100644 --- a/openfpga/src/fpga_spice/spice_api.cpp +++ b/openfpga/src/fpga_spice/spice_api.cpp @@ -39,7 +39,7 @@ namespace openfpga { ********************************************************************/ int fpga_fabric_spice(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const Arch& openfpga_arch, const FabricSpiceOption& options) { vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n"); @@ -71,7 +71,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager, int status = CMD_EXEC_SUCCESS; status = print_spice_submodule(netlist_manager, - tech_lib, + module_manager, + openfpga_arch, submodule_dir_path); if (CMD_EXEC_SUCCESS != status) { diff --git a/openfpga/src/fpga_spice/spice_api.h b/openfpga/src/fpga_spice/spice_api.h index a214ac652..cf1ce5a0a 100644 --- a/openfpga/src/fpga_spice/spice_api.h +++ b/openfpga/src/fpga_spice/spice_api.h @@ -9,7 +9,7 @@ #include #include "netlist_manager.h" #include "module_manager.h" -#include "technology_library.h" +#include "openfpga_arch.h" #include "fabric_spice_options.h" /******************************************************************** @@ -21,7 +21,7 @@ namespace openfpga { int fpga_fabric_spice(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const Arch& openfpga_arch, const FabricSpiceOption& options); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp index b21b98b59..7fd144f33 100644 --- a/openfpga/src/fpga_spice/spice_essential_gates.cpp +++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp @@ -5,6 +5,7 @@ * logic gates etc. ***********************************************/ #include +#include #include /* Headers from vtrutil library */ @@ -17,15 +18,18 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" +#include "circuit_library_utils.h" + #include "spice_constants.h" +#include "spice_writer_utils.h" #include "spice_essential_gates.h" /* begin namespace openfpga */ namespace openfpga { -/************************************************ +/******************************************************************** * Print a SPICE model wrapper for a transistor model - ***********************************************/ + *******************************************************************/ static int print_spice_transistor_model_wrapper(std::fstream& fp, const TechnologyLibrary& tech_lib, @@ -66,9 +70,9 @@ int print_spice_transistor_model_wrapper(std::fstream& fp, return CMD_EXEC_SUCCESS; } -/************************************************ +/******************************************************************** * Generate the SPICE netlist for transistors - ***********************************************/ + *******************************************************************/ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, const TechnologyLibrary& tech_lib, const std::string& submodule_dir) { @@ -82,9 +86,11 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, check_file_stream(spice_fname.c_str(), fp); /* Create file */ - VTR_LOG("Generating SPICE netlist '%s' for transistor wrappers...", + VTR_LOG("Generating SPICE netlist '%s' for transistors...", spice_fname.c_str()); + print_spice_file_header(fp, std::string("Transistor wrappers")); + /* Iterate over the transistor models */ for (const TechnologyModelId& model : tech_lib.models()) { /* Focus on transistor model */ @@ -110,4 +116,972 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Generate the SPICE modeling for a power-gated inverter + * + * This function is created to be shared by inverter and buffer SPICE netlist writer + * + * Note: + * - This function does NOT create a file + * but requires a file stream created + * - This function only output SPICE modeling for + * an inverter. Any preprocessing or subckt definition should not be included! + *******************************************************************/ +static +int print_spice_powergated_inverter_pmos_modeling(std::fstream& fp, + const std::string& trans_name_postfix, + const std::string& input_port_name, + const std::string& output_port_name, + const CircuitLibrary& circuit_lib, + const CircuitPortId& enb_port, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model, + const float& trans_width) { + + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Write power-gating transistor pairs using the technology model + * Note that for a mulit-bit power gating port, we should cascade the transistors + */ + bool first_enb_pin = true; + size_t last_enb_pin; + for (const auto& power_gate_pin : circuit_lib.pins(enb_port)) { + BasicPort enb_pin(circuit_lib.port_prefix(enb_port), power_gate_pin, power_gate_pin); + fp << "Xpmos_powergate_" << trans_name_postfix << "_pin_" << power_gate_pin << " "; + /* For the first pin, we should connect it to local VDD*/ + if (true == first_enb_pin) { + fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; + fp << generate_spice_port(enb_pin) << " "; + fp << "LVDD "; + fp << "LVDD "; + first_enb_pin = false; + } else { + VTR_ASSERT_SAFE(false == first_enb_pin); + fp << output_port_name << "_pmos_pg_" << last_enb_pin << " "; + fp << generate_spice_port(enb_pin) << " "; + fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; + fp << "LVDD "; + } + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; + fp << " W=" << std::setprecision(10) << trans_width; + fp << "\n"; + + /* Cache the last pin*/ + last_enb_pin = power_gate_pin; + } + + /* Write transistor pairs using the technology model */ + fp << "Xpmos_" << trans_name_postfix << " "; + fp << output_port_name << " "; + fp << input_port_name << " "; + fp << output_port_name << "_pmos_pg_" << circuit_lib.pins(enb_port).back() << " "; + fp << "LVDD "; + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; + fp << " W=" << std::setprecision(10) << trans_width; + fp << "\n"; + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Generate the SPICE modeling for the NMOS part of a power-gated inverter + * + * This function is created to be shared by inverter and buffer SPICE netlist writer + * + * Note: + * - This function does NOT create a file + * but requires a file stream created + * - This function only output SPICE modeling for + * an inverter. Any preprocessing or subckt definition should not be included! + *******************************************************************/ +static +int print_spice_powergated_inverter_nmos_modeling(std::fstream& fp, + const std::string& trans_name_postfix, + const std::string& input_port_name, + const std::string& output_port_name, + const CircuitLibrary& circuit_lib, + const CircuitPortId& en_port, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model, + const float& trans_width) { + + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + bool first_en_pin = true; + size_t last_en_pin; + for (const auto& power_gate_pin : circuit_lib.pins(en_port)) { + BasicPort en_pin(circuit_lib.port_prefix(en_port), power_gate_pin, power_gate_pin); + fp << "Xnmos_powergate_" << trans_name_postfix << "_pin_" << power_gate_pin << " "; + /* For the first pin, we should connect it to local VDD*/ + if (true == first_en_pin) { + fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; + fp << generate_spice_port(en_pin) << " "; + fp << "LGND "; + fp << "LGND "; + first_en_pin = false; + } else { + VTR_ASSERT_SAFE(false == first_en_pin); + fp << output_port_name << "_nmos_pg_" << last_en_pin << " "; + fp << circuit_lib.port_prefix(en_port) << " "; + fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; + fp << "LGND "; + } + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; + fp << " W=" << std::setprecision(10) << trans_width; + fp << "\n"; + + /* Cache the last pin*/ + last_en_pin = power_gate_pin; + } + + fp << "Xnmos_" << trans_name_postfix << " "; + fp << output_port_name << " "; + fp << input_port_name << " "; + fp << output_port_name << " _nmos_pg_" << circuit_lib.pins(en_port).back() << " "; + fp << "LGND "; + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; + fp << " W=" << std::setprecision(10) << trans_width; + fp << "\n"; + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Generate the SPICE subckt for a power gated inverter + * The Enable signal controlled the power gating + * + * Note: + * - This function supports multi-bit power gating + * + * Schematic + * LVDD + * | + * - + * ENb[0] -o|| + * - + * | + * - + * ENb[1] -o|| + * - + * | + * + * ... + * + * | + * - + * +-o|| + * | - + * | | + * in-->+ +--> OUT + * | | + * | - + * +--|| + * - + * + * ... + * + * | + * - + * EN[1] -|| + * - + * | + * - + * EN[0] -|| + * - + * | + * LGND + * + *******************************************************************/ +static +int print_spice_powergated_inverter_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Print the inverter subckt definition */ + print_spice_subckt_definition(fp, module_manager, module_id); + + /* Find the input and output ports: + * we do NOT support global ports here, + * it should be handled in another type of inverter subckt (power-gated) + */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ + VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model)); + CircuitPortId en_port = find_circuit_model_power_gate_en_port(circuit_lib, circuit_model); + CircuitPortId enb_port = find_circuit_model_power_gate_enb_port(circuit_lib, circuit_model); + VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(en_port)); + VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(enb_port)); + + int status = CMD_EXEC_SUCCESS; + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + float total_pmos_width = circuit_lib.buffer_size(circuit_model) + * tech_lib.model_pn_ratio(tech_model) + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width); + float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width); + for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { + float curr_bin_width = regular_pmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_pmos_bins - 1) + && (0. != last_pmos_bin_width)) { + curr_bin_width = last_pmos_bin_width; + } + status = print_spice_powergated_inverter_pmos_modeling(fp, + std::to_string(ibin), + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + circuit_lib, + enb_port, + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + float total_nmos_width = circuit_lib.buffer_size(circuit_model) + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width); + float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width); + for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { + float curr_bin_width = regular_nmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_nmos_bins - 1) + && (0. != last_nmos_bin_width)) { + curr_bin_width = last_nmos_bin_width; + } + + status = print_spice_powergated_inverter_nmos_modeling(fp, + std::to_string(ibin), + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + circuit_lib, + en_port, + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + + print_spice_subckt_end(fp, module_manager.module_name(module_id)); + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Generate the SPICE modeling for the PMOS part of a regular inverter + * + * This function is created to be shared by inverter and buffer SPICE netlist writer + * + * Note: + * - This function does NOT create a file + * but requires a file stream created + * - This function only output SPICE modeling for + * an inverter. Any preprocessing or subckt definition should not be included! + *******************************************************************/ +static +int print_spice_regular_inverter_pmos_modeling(std::fstream& fp, + const std::string& trans_name_postfix, + const std::string& input_port_name, + const std::string& output_port_name, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model, + const float& trans_width) { + + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Write transistor pairs using the technology model */ + fp << "Xpmos_" << trans_name_postfix << " "; + fp << output_port_name << " "; + fp << input_port_name << " "; + fp << "LVDD "; + fp << "LVDD "; + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; + fp << " W=" << std::setprecision(10) << trans_width; + fp << "\n"; + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Generate the SPICE modeling for the NMOS part of a regular inverter + * + * This function is created to be shared by inverter and buffer SPICE netlist writer + * + * Note: + * - This function does NOT create a file + * but requires a file stream created + * - This function only output SPICE modeling for + * an inverter. Any preprocessing or subckt definition should not be included! + *******************************************************************/ +static +int print_spice_regular_inverter_nmos_modeling(std::fstream& fp, + const std::string& trans_name_postfix, + const std::string& input_port_name, + const std::string& output_port_name, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model, + const float& trans_width) { + + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + fp << "Xnmos_" << trans_name_postfix << " "; + fp << output_port_name << " "; + fp << input_port_name << " "; + fp << "LGND "; + fp << "LGND "; + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; + fp << " W=" << std::setprecision(10) << trans_width; + fp << "\n"; + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Generate the SPICE subckt for a regular inverter + * + * Note: + * - This function does NOT support power-gating + * It should be managed in a separated function + * + * Schematic + * LVDD + * | + * - + * +-o|| + * | - + * | | + * in-->+ +--> OUT + * | | + * | - + * +--|| + * - + * | + * LGND + * + *******************************************************************/ +static +int print_spice_regular_inverter_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Print the inverter subckt definition */ + print_spice_subckt_definition(fp, module_manager, module_id); + + /* Find the input and output ports: + * we do NOT support global ports here, + * it should be handled in another type of inverter subckt (power-gated) + */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + int status = CMD_EXEC_SUCCESS; + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + float total_pmos_width = circuit_lib.buffer_size(circuit_model) + * tech_lib.model_pn_ratio(tech_model) + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width); + float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width); + for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { + float curr_bin_width = regular_pmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_pmos_bins - 1) + && (0. != last_pmos_bin_width)) { + curr_bin_width = last_pmos_bin_width; + } + + status = print_spice_regular_inverter_pmos_modeling(fp, + std::to_string(ibin), + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + float total_nmos_width = circuit_lib.buffer_size(circuit_model) + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width); + float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width); + + for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { + float curr_bin_width = regular_nmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_nmos_bins - 1) + && (0. != last_nmos_bin_width)) { + curr_bin_width = last_nmos_bin_width; + } + + status = print_spice_regular_inverter_nmos_modeling(fp, + std::to_string(ibin), + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + + print_spice_subckt_end(fp, module_manager.module_name(module_id)); + + return status; +} + +/******************************************************************** + * Generate the SPICE subckt for an inverter + * Branch on the different circuit topologies + *******************************************************************/ +static +int print_spice_inverter_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + int status = CMD_EXEC_SUCCESS; + if (true == circuit_lib.is_power_gated(circuit_model)) { + status = print_spice_powergated_inverter_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } else { + VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model)); + status = print_spice_regular_inverter_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } + + return status; +} + +/******************************************************************** + * Generate the SPICE subckt for a power-gated buffer + * which contains at least 2 stages + * + * Schematic of a multi-stage buffer + * + * LVDD LVDD + * | | + * - - + * ENb[0] -o|| ENb[0] -o|| + * - - + * | | + * - - + * ENb[1] -o|| ENb[1] -o|| + * - - + * | | + * + * ... + * + * | | + * - - + * +-o|| +-o|| + * | - | - + * | | | | + * in-->+ +-- ... ---+---->+---> out + * | | | | + * | - | - + * +--|| +--|| + * - - + * | | + * + * ... + * + * | | + * - - + * EN[0] -|| EN[0] -|| + * - - + * | | + * - - + * EN[1] -|| EN[1] -|| + * - - + * | | + + * | | + * LGND LGND + * + *******************************************************************/ +static +int print_spice_powergated_buffer_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Print the inverter subckt definition */ + print_spice_subckt_definition(fp, module_manager, module_id); + + /* Find the input and output ports: + * we do NOT support global ports here, + * it should be handled in another type of inverter subckt (power-gated) + */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ + VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model)); + CircuitPortId en_port = find_circuit_model_power_gate_en_port(circuit_lib, circuit_model); + CircuitPortId enb_port = find_circuit_model_power_gate_enb_port(circuit_lib, circuit_model); + VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(en_port)); + VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(enb_port)); + + int status = CMD_EXEC_SUCCESS; + + /* Buffers must have >= 2 stages */ + VTR_ASSERT(2 <= circuit_lib.buffer_num_levels(circuit_model)); + + /* Build the array denoting width of inverters per stage */ + std::vector buffer_widths(circuit_lib.buffer_num_levels(circuit_model), 1); + for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) { + buffer_widths[level] = circuit_lib.buffer_size(circuit_model) + * std::pow(circuit_lib.buffer_f_per_stage(circuit_model), level); + } + + for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) { + std::string input_port_name = circuit_lib.port_prefix(input_ports[0]); + std::string output_port_name = circuit_lib.port_prefix(output_ports[0]); + + /* Special for first stage: output port should be an intermediate node + * Special for rest of stages: input port should be the output of previous stage + */ + if (0 == level) { + output_port_name += std::string("_level") + std::to_string(level); + } else { + VTR_ASSERT(0 < level); + input_port_name += std::string("_level") + std::to_string(level - 1); + } + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + float total_pmos_width = buffer_widths[level] + * tech_lib.model_pn_ratio(tech_model) + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width); + float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width); + + for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { + float curr_bin_width = regular_pmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_pmos_bins - 1) + && (0. != last_pmos_bin_width)) { + curr_bin_width = last_pmos_bin_width; + } + + std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin); + + status = print_spice_powergated_inverter_pmos_modeling(fp, + name_postfix, + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + circuit_lib, + enb_port, + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + float total_nmos_width = buffer_widths[level] + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width); + float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width); + + for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { + float curr_bin_width = regular_nmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_nmos_bins - 1) + && (0. != last_nmos_bin_width)) { + curr_bin_width = last_nmos_bin_width; + } + + std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin); + + status = print_spice_powergated_inverter_nmos_modeling(fp, + name_postfix, + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + circuit_lib, + en_port, + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + } + + print_spice_subckt_end(fp, module_manager.module_name(module_id)); + + return CMD_EXEC_SUCCESS; +} + + +/******************************************************************** + * Generate the SPICE subckt for a regular buffer + * which contains at least 2 stages + * + * Note: + * - This function does NOT support power-gating + * It should be managed in a separated function + * + * Schematic of a multi-stage buffer + * + * LVDD LVDD + * | | + * - - + * +-o|| +-o|| + * | - | - + * | | | | + * in-->+ +-- ... ---+---->+---> out + * | | | | + * | - | - + * +--|| +--|| + * - - + * | | + * LGND LGND + * + *******************************************************************/ +static +int print_spice_regular_buffer_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Print the inverter subckt definition */ + print_spice_subckt_definition(fp, module_manager, module_id); + + /* Find the input and output ports: + * we do NOT support global ports here, + * it should be handled in another type of inverter subckt (power-gated) + */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + int status = CMD_EXEC_SUCCESS; + + /* Buffers must have >= 2 stages */ + VTR_ASSERT(2 <= circuit_lib.buffer_num_levels(circuit_model)); + + /* Build the array denoting width of inverters per stage */ + std::vector buffer_widths(circuit_lib.buffer_num_levels(circuit_model), 1); + for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) { + buffer_widths[level] = circuit_lib.buffer_size(circuit_model) + * std::pow(circuit_lib.buffer_f_per_stage(circuit_model), level); + } + + for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) { + std::string input_port_name = circuit_lib.port_prefix(input_ports[0]); + std::string output_port_name = circuit_lib.port_prefix(output_ports[0]); + + /* Special for first stage: output port should be an intermediate node + * Special for rest of stages: input port should be the output of previous stage + */ + if (0 == level) { + output_port_name += std::string("_level") + std::to_string(level); + } else { + VTR_ASSERT(0 < level); + input_port_name += std::string("_level") + std::to_string(level - 1); + } + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + float total_pmos_width = buffer_widths[level] + * tech_lib.model_pn_ratio(tech_model) + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS); + int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width); + float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width); + + for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { + float curr_bin_width = regular_pmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_pmos_bins - 1) + && (0. != last_pmos_bin_width)) { + curr_bin_width = last_pmos_bin_width; + } + + std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin); + + status = print_spice_regular_inverter_pmos_modeling(fp, + name_postfix, + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + + /* Consider use size/bin to compact layout: + * Try to size transistors to the max width for each bin + * The last bin may not reach the max width + */ + float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + float total_nmos_width = buffer_widths[level] + * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS); + int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width); + float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width); + + for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { + float curr_bin_width = regular_nmos_bin_width; + /* For last bin, we need an irregular width */ + if ((ibin == num_nmos_bins - 1) + && (0. != last_nmos_bin_width)) { + curr_bin_width = last_nmos_bin_width; + } + + std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin); + + status = print_spice_regular_inverter_nmos_modeling(fp, + name_postfix, + circuit_lib.port_prefix(input_ports[0]), + circuit_lib.port_prefix(output_ports[0]), + tech_lib, + tech_model, + curr_bin_width); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + } + } + + print_spice_subckt_end(fp, module_manager.module_name(module_id)); + + return status; +} + +/******************************************************************** + * Generate the SPICE subckt for an buffer + * which consists of multiple stage of inverters + *******************************************************************/ +static +int print_spice_buffer_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + int status = CMD_EXEC_SUCCESS; + if (true == circuit_lib.is_power_gated(circuit_model)) { + status = print_spice_powergated_buffer_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } else { + VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model)); + status = print_spice_regular_buffer_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } + + return status; +} + +/******************************************************************** + * Generate the SPICE netlist for essential gates: + * - inverters and their templates + * - buffers and their templates + * - pass-transistor or transmission gates + * - logic gates + *******************************************************************/ +int print_spice_essential_gates(NetlistManager& netlist_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const TechnologyLibrary& tech_lib, + const std::map& circuit_tech_binding, + const std::string& submodule_dir) { + std::string spice_fname = submodule_dir + std::string(ESSENTIALS_SPICE_FILE_NAME); + + std::fstream fp; + + /* Create the file stream */ + fp.open(spice_fname, std::fstream::out | std::fstream::trunc); + /* Check if the file stream if valid or not */ + check_file_stream(spice_fname.c_str(), fp); + + /* Create file */ + VTR_LOG("Generating SPICE netlist '%s' for essential gates...", + spice_fname.c_str()); + + print_spice_file_header(fp, std::string("Essential gates")); + + int status = CMD_EXEC_SUCCESS; + + /* Iterate over the circuit models */ + for (const CircuitModelId& circuit_model : circuit_lib.models()) { + /* Bypass models require extern netlists */ + if (!circuit_lib.model_circuit_netlist(circuit_model).empty()) { + continue; + } + + /* Spot module id */ + const ModuleId& module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); + + TechnologyModelId tech_model; + /* Focus on inverter/buffer/pass-gate/logic gates only */ + if ( (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) + || (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) + || (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model))) { + auto result = circuit_tech_binding.find(circuit_model); + if (result == circuit_tech_binding.end()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Unable to find technology binding for circuit model '%s'!\n", + circuit_lib.model_name(circuit_model).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + /* Valid technology binding. Assign techology model */ + tech_model = result->second; + /* Ensure we have a valid technology model */ + VTR_ASSERT(true == tech_lib.valid_model_id(tech_model)); + VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == tech_lib.model_type(tech_model)); + } + + /* Now branch on netlist writing */ + if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { + if (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) { + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); + status = print_spice_inverter_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } else { + VTR_ASSERT(CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)); + status = print_spice_buffer_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } + + if (CMD_EXEC_FATAL_ERROR == status) { + break; + } + + /* Finish, go to the next */ + continue; + } + } + + /* Close file handler*/ + fp.close(); + + /* Add fname to the netlist name list */ + NetlistId nlist_id = netlist_manager.add_netlist(spice_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); + + VTR_LOG("Done\n"); + + return status; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_spice/spice_essential_gates.h b/openfpga/src/fpga_spice/spice_essential_gates.h index 055a8a55f..de9ab3cdb 100644 --- a/openfpga/src/fpga_spice/spice_essential_gates.h +++ b/openfpga/src/fpga_spice/spice_essential_gates.h @@ -5,7 +5,10 @@ * Include header files that are required by function declaration *******************************************************************/ #include +#include #include "netlist_manager.h" +#include "module_manager.h" +#include "circuit_library.h" #include "technology_library.h" /******************************************************************** @@ -19,6 +22,13 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, const TechnologyLibrary& tech_lib, const std::string& submodule_dir); +int print_spice_essential_gates(NetlistManager& netlist_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const TechnologyLibrary& tech_lib, + const std::map& circuit_tech_binding, + const std::string& submodule_dir); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp index e99a0feda..4de678af5 100644 --- a/openfpga/src/fpga_spice/spice_submodule.cpp +++ b/openfpga/src/fpga_spice/spice_submodule.cpp @@ -28,15 +28,23 @@ namespace openfpga { * 6. TODO: Configuration memory blocks ********************************************************************/ int print_spice_submodule(NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const ModuleManager& module_manager, + const Arch& openfpga_arch, const std::string& submodule_dir) { int status = CMD_EXEC_SUCCESS; status = print_spice_transistor_wrapper(netlist_manager, - tech_lib, + openfpga_arch.tech_lib, submodule_dir); + status = print_spice_essential_gates(netlist_manager, + module_manager, + openfpga_arch.circuit_lib, + openfpga_arch.tech_lib, + openfpga_arch.circuit_tech_binding, + submodule_dir); + return status; } diff --git a/openfpga/src/fpga_spice/spice_submodule.h b/openfpga/src/fpga_spice/spice_submodule.h index bea004b6d..27a49de87 100644 --- a/openfpga/src/fpga_spice/spice_submodule.h +++ b/openfpga/src/fpga_spice/spice_submodule.h @@ -5,7 +5,8 @@ * Include header files that are required by function declaration *******************************************************************/ #include "netlist_manager.h" -#include "technology_library.h" +#include "module_manager.h" +#include "openfpga_arch.h" /******************************************************************** * Function declaration @@ -15,7 +16,8 @@ namespace openfpga { int print_spice_submodule(NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const ModuleManager& module_manager, + const Arch& openfpga_arch, const std::string& submodule_dir); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index cb8eb9504..d33407071 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -45,14 +45,15 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, /* Create a sensitive list */ fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; - fp << "\talways @(" << std::endl; + fp << "\talways @("; /* Power-gate port first*/ for (const auto& power_gate_port : power_gate_ports) { - /* Skip first comma to dump*/ - if (0 < &power_gate_port - &power_gate_ports[0]) { - fp << ","; + /* Only config_enable signal will be considered */ + if (false == circuit_lib.port_is_config_enable(power_gate_port)) { + continue; } fp << circuit_lib.port_prefix(power_gate_port); + fp << ", "; } fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; @@ -61,6 +62,10 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, /* For the first pin, we skip output comma */ size_t port_cnt = 0; for (const auto& power_gate_port : power_gate_ports) { + /* Only config_enable signal will be considered */ + if (false == circuit_lib.port_is_config_enable(power_gate_port)) { + continue; + } for (const auto& power_gate_pin : circuit_lib.pins(power_gate_port)) { if (0 < port_cnt) { fp << std::endl << "\t\t&&"; @@ -70,7 +75,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, /* Power-gated signal are disable during operating, enabled during configuration, * Therefore, we need to reverse them here */ - if (0 == circuit_lib.port_default_value(power_gate_port)) { + if (1 == circuit_lib.port_default_value(power_gate_port)) { fp << "~"; } @@ -161,30 +166,6 @@ void print_verilog_invbuf_module(const ModuleManager& module_manager, VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - /* TODO: move the check codes to check_circuit_library.h */ - /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ - if (true == circuit_lib.is_power_gated(circuit_model)) { - /* Check all the ports we have are good for a power-gated circuit model */ - size_t num_err = 0; - /* We need at least one global port */ - if (0 == global_ports.size()) { - num_err++; - } - /* All the global ports should be config_enable */ - for (const auto& port : global_ports) { - if (false == circuit_lib.port_is_config_enable(port)) { - num_err++; - } - } - /* Report errors if there are any */ - if (0 < num_err) { - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n", - circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - } - /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); VTR_ASSERT(true == module_manager.valid_module_id(module_id)); diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index d2917836b..35af744e6 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -63,14 +63,12 @@ namespace openfpga { * *******************************************************************/ static -void print_verilog_primitive_block(std::fstream& fp, +void print_verilog_primitive_block(NetlistManager& netlist_manager, const ModuleManager& module_manager, + const std::string& subckt_dir, t_pb_graph_node* primitive_pb_graph_node, const bool& use_explicit_mapping, const bool& verbose) { - /* Ensure a valid file handler */ - VTR_ASSERT(true == valid_file_stream(fp)); - /* Ensure a valid pb_graph_node */ if (nullptr == primitive_pb_graph_node) { VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -78,6 +76,24 @@ void print_verilog_primitive_block(std::fstream& fp, exit(1); } + /* Give a name to the Verilog netlist */ + /* Create the file name for Verilog */ + std::string verilog_fname(subckt_dir + + generate_logical_tile_netlist_name(std::string(), primitive_pb_graph_node, std::string(VERILOG_NETLIST_FILE_POSTFIX)) + ); + + VTR_LOG("Writing Verilog netlist '%s' for primitive pb_type '%s' ...", + verilog_fname.c_str(), primitive_pb_graph_node->pb_type->name); + VTR_LOGV(verbose, "\n"); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(verilog_fname.c_str(), fp); + + print_verilog_file_header(fp, std::string("Verilog modules for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name))); + /* Generate the module name for this primitive pb_graph_node*/ std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type); @@ -93,8 +109,13 @@ void print_verilog_primitive_block(std::fstream& fp, /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping); - /* Add an empty line as a splitter */ - fp << std::endl; + /* Close file handler */ + fp.close(); + + /* Add fname to the netlist name list */ + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST); VTR_LOGV(verbose, "Done\n"); } @@ -115,14 +136,13 @@ void print_verilog_primitive_block(std::fstream& fp, * to its parent in module manager *******************************************************************/ static -void rec_print_verilog_logical_tile(std::fstream& fp, +void rec_print_verilog_logical_tile(NetlistManager& netlist_manager, const ModuleManager& module_manager, const VprDeviceAnnotation& device_annotation, + const std::string& subckt_dir, t_pb_graph_node* physical_pb_graph_node, const bool& use_explicit_mapping, const bool& verbose) { - /* Check the file handler*/ - VTR_ASSERT(true == valid_file_stream(fp)); /* Check cur_pb_graph_node*/ if (nullptr == physical_pb_graph_node) { @@ -143,8 +163,9 @@ void rec_print_verilog_logical_tile(std::fstream& fp, if (false == is_primitive_pb_type(physical_pb_type)) { for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) { /* Go recursive to visit the children */ - rec_print_verilog_logical_tile(fp, - module_manager, device_annotation, + rec_print_verilog_logical_tile(netlist_manager, + module_manager, device_annotation, + subckt_dir, &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]), use_explicit_mapping, verbose); @@ -156,7 +177,9 @@ void rec_print_verilog_logical_tile(std::fstream& fp, * explict port mapping. This aims to avoid any port sequence issues!!! */ if (true == is_primitive_pb_type(physical_pb_type)) { - print_verilog_primitive_block(fp, module_manager, + print_verilog_primitive_block(netlist_manager, + module_manager, + subckt_dir, physical_pb_graph_node, true, verbose); @@ -164,6 +187,24 @@ void rec_print_verilog_logical_tile(std::fstream& fp, return; } + /* Give a name to the Verilog netlist */ + /* Create the file name for Verilog */ + std::string verilog_fname(subckt_dir + + generate_logical_tile_netlist_name(std::string(), physical_pb_graph_node, std::string(VERILOG_NETLIST_FILE_POSTFIX)) + ); + + VTR_LOG("Writing Verilog netlist '%s' for pb_type '%s' ...", + verilog_fname.c_str(), physical_pb_type->name); + VTR_LOGV(verbose, "\n"); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(verilog_fname.c_str(), fp); + + print_verilog_file_header(fp, std::string("Verilog modules for pb_type: " + std::string(physical_pb_type->name))); + /* Generate the name of the Verilog module for this pb_type */ std::string pb_module_name = generate_physical_block_module_name(physical_pb_type); @@ -172,7 +213,7 @@ void rec_print_verilog_logical_tile(std::fstream& fp, VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); VTR_LOGV(verbose, - "Writing Verilog codes of logical tile block '%s'...", + "Writing Verilog codes of pb_type '%s'...", module_manager.module_name(pb_module).c_str()); /* Comment lines */ @@ -183,8 +224,13 @@ void rec_print_verilog_logical_tile(std::fstream& fp, print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); - /* Add an empty line as a splitter */ - fp << std::endl; + /* Close file handler */ + fp.close(); + + /* Add fname to the netlist name list */ + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST); VTR_LOGV(verbose, "Done\n"); } @@ -201,23 +247,10 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, t_pb_graph_node* pb_graph_head, const bool& use_explicit_mapping, const bool& verbose) { - /* Give a name to the Verilog netlist */ - /* Create the file name for Verilog */ - std::string verilog_fname(subckt_dir - + generate_logical_tile_netlist_name(std::string(LOGICAL_MODULE_VERILOG_FILE_NAME_PREFIX), pb_graph_head, std::string(VERILOG_NETLIST_FILE_POSTFIX)) - ); - VTR_LOG("Writing Verilog netlist '%s' for logic tile '%s' ...", - verilog_fname.c_str(), pb_graph_head->pb_type->name); - VTR_LOGV(verbose, "\n"); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_stream(verilog_fname.c_str(), fp); - - print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]")); + VTR_LOG("Writing Verilog netlists for logic tile '%s' ...", + pb_graph_head->pb_type->name); + VTR_LOG("\n"); /* Print Verilog modules for all the pb_types/pb_graph_nodes * use a Depth-First Search Algorithm to print the sub-modules @@ -226,23 +259,14 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, * to its parent in module manager */ /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ - rec_print_verilog_logical_tile(fp, module_manager, + rec_print_verilog_logical_tile(netlist_manager, + module_manager, device_annotation, + subckt_dir, pb_graph_head, use_explicit_mapping, verbose); - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the netlist name list */ - NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); - VTR_ASSERT(NetlistId::INVALID() != nlist_id); - netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST); - VTR_LOG("Done\n"); VTR_LOG("\n"); } @@ -270,7 +294,7 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager, /* Give a name to the Verilog netlist */ /* Create the file name for Verilog */ std::string verilog_fname(subckt_dir - + generate_grid_block_netlist_name(std::string(phy_block_type->name), + + generate_grid_block_netlist_name(std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name), is_io_type(phy_block_type), border_side, std::string(VERILOG_NETLIST_FILE_POSTFIX)) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 0f5640618..27f714957 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1154,17 +1154,18 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, /* Attention: when the fast configuration is enabled, we will start from the first bit '1' * This requires a reset signal (as we forced in the first clock cycle) */ - bool first_bit_one = false; + bool start_config = false; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { - first_bit_one = true; + if ( (false == start_config) + && (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { + start_config = true; } /* In fast configuration mode, we do not output anything * until we have to (the first bit '1' detected) */ if ( (true == fast_configuration) - && (false == first_bit_one)) { + && (false == start_config)) { continue; } diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp index 07ef140a3..cd59545ae 100644 --- a/openfpga/src/utils/circuit_library_utils.cpp +++ b/openfpga/src/utils/circuit_library_utils.cpp @@ -287,4 +287,62 @@ bool check_configurable_memory_circuit_model(const e_config_protocol_type& confi return (0 == num_err); } +/************************************************************************ + * Try to find the enable port control power-gate for a power-gated circuit model + * We will return the first port that meet the requirement: + * - a global port + * - its function is labelled as config_enable + * - default value is 0 + * Return invalid id if not found + ***********************************************************************/ +CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model)); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true); + + /* Try to find an ENABLE port from the global ports */ + CircuitPortId en_port = CircuitPortId::INVALID(); + for (const auto& port : global_ports) { + /* Focus on config_enable ports which are power-gate control signals */ + if (false == circuit_lib.port_is_config_enable(port)) { + continue; + } + if (1 == circuit_lib.port_default_value(port)) { + en_port = port; + break; + } + } + + return en_port; +} + +/************************************************************************ + * Try to find the enableB port control power-gate for a power-gated circuit model + * We will return the first port that meet the requirement: + * - a global port + * - its function is labelled as config_enable + * - default value is 1 + * Return invalid id if not found + ***********************************************************************/ +CircuitPortId find_circuit_model_power_gate_enb_port(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + CircuitPortId enb_port = CircuitPortId::INVALID(); + VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model)); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true); + + /* Try to find an ENABLE_B port from the global ports */ + for (const auto& port : global_ports) { + /* Focus on config_enable ports which are power-gate control signals */ + if (false == circuit_lib.port_is_config_enable(port)) { + continue; + } + if (0 == circuit_lib.port_default_value(port)) { + enb_port = port; + break; + } + } + + return enb_port; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h index 255da4f4f..584871868 100644 --- a/openfpga/src/utils/circuit_library_utils.h +++ b/openfpga/src/utils/circuit_library_utils.h @@ -43,6 +43,12 @@ bool check_configurable_memory_circuit_model(const e_config_protocol_type& confi const CircuitLibrary& circuit_lib, const CircuitModelId& config_mem_circuit_model); +CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +CircuitPortId find_circuit_model_power_gate_enb_port(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + } /* end namespace openfpga */ #endif diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga index 33891b72d..d9391c4c1 100644 --- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga @@ -37,10 +37,13 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream -build_fabric_bitstream --verbose +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga index 97f540116..f507fc49c 100644 --- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga @@ -37,10 +37,13 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream -build_fabric_bitstream --verbose +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga index 97f540116..a9f20d9d8 100644 --- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga @@ -37,11 +37,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga index d6800e2f1..43e62f7a4 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga @@ -37,10 +37,13 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream -build_fabric_bitstream --verbose +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index e5cb63413..d1c20fb9d 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -37,11 +37,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga index 97f540116..a9f20d9d8 100644 --- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga @@ -37,11 +37,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga index e7c934513..ab79ce90a 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga @@ -35,10 +35,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream -build_fabric_bitstream --verbose +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.txt --format plain_text +write_fabric_bitstream --file fabric_bitstream.xml --format xml # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga index d98e9b74d..7993838cd 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga @@ -40,11 +40,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga index 47b3edce3..15098c124 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga @@ -40,11 +40,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga new file mode 100644 index 000000000..3b50edbc8 --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga @@ -0,0 +1,35 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_spice --file ./SPICE --verbose + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga index a0e09687f..8cfb063d1 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga @@ -37,11 +37,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream --format xml + # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists # - Must specify the reference benchmark file if you want to output any testbenches diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga index ed7ccf1de..7dbab86a5 100644 --- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga @@ -37,11 +37,14 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga new file mode 100644 index 000000000..f53e6b187 --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga @@ -0,0 +1,77 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Read external bitstream from a file which will overwrite the VPR results +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose \ + --read_file ${OPENFPGA_EXTERNAL_ARCH_BITSTREAM_FILE} \ + --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v new file mode 100644 index 000000000..f976a60d6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v @@ -0,0 +1,81 @@ +module FSM_hour( + input wire rst, + input wire clk, + input wire [5:0] hour_in, + input wire hour_in_load, + input wire [5:0] min_count, + input wire [5:0] sec_count, + output reg [5:0] hour_out); + + reg [2:0] ps, ns; + wire [5:0] hour_data_add; + reg [5:0] hour_data; + reg [5:0] hour_ps, hour_ns; + reg [1:0] hour_sel; + wire hour_count; + + always@(posedge clk) + begin + if(rst) ps <= 3'd0; + else ps <= ns; + end + + always@(posedge clk) + begin + if(rst) hour_ps <= 6'd0; + else hour_ps <= hour_ns; + end + + always@(*) + begin + hour_sel = 2'd0; + case(ps) + 3'd0: begin + ns = 3'd1; + end + 3'd1: begin + if(hour_in_load) begin + hour_sel = 2'd1; + hour_out = hour_data; + ns = 3'd2; + hour_ns = hour_data; + end + else ns = 3'd1; + end + 3'd2: begin + if(hour_count == 1'd1) begin + if(hour_data == 6'd59) begin + hour_out = hour_data; + ns = 3'd2; + hour_ns = 6'd0; + end + else begin + hour_out = hour_data; + ns = 3'd2; + hour_ns = hour_data_add; + end + end + else begin + hour_out = hour_data; + hour_ns = hour_data; + ns = 3'd2; + end + end + default: begin + ns = 3'd0; + end + endcase + end + + assign hour_data_add = hour_data + 1; + assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0; + + always@(*) + begin + case(hour_sel) + 2'd0: hour_data = hour_ps; + 2'd1: hour_data = hour_in; + endcase + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v new file mode 100644 index 000000000..0f67682ad --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v @@ -0,0 +1,80 @@ +module FSM_minute( + input wire rst, + input wire clk, + input wire [5:0] min_in, + input wire min_in_load, + input wire [5:0] sec_count, + output reg [5:0] min_out); + + reg [2:0] ps, ns; + wire [5:0] min_data_add; + reg [5:0] min_data; + reg [5:0] min_ps, min_ns; + reg [1:0] min_sel; + wire min_count; + + always@(posedge clk) + begin + if(rst) ps <= 3'd0; + else ps <= ns; + end + + always@(posedge clk) + begin + if(rst) min_ps <= 6'd0; + else min_ps <= min_ns; + end + + always@(*) + begin + min_sel = 2'd0; + case(ps) + 3'd0: begin + ns = 3'd1; + end + 3'd1: begin + if(min_in_load) begin + min_sel = 2'd1; + min_out = min_data; + ns = 3'd2; + min_ns = min_data; + end + else ns = 3'd1; + end + 3'd2: begin + if(min_count == 1'd1) begin + if(min_data == 6'd59) begin + min_out = min_data; + ns = 3'd2; + min_ns = 6'd0; + end + else begin + min_out = min_data; + ns = 3'd2; + min_ns = min_data_add; + end + end + else begin + min_out = min_data; + min_ns = min_data; + ns = 3'd2; + end + end + default: begin + ns = 3'd0; + end + endcase + end + + assign min_data_add = min_data + 1; + assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0; + + always@(*) + begin + case(min_sel) + 2'd0: min_data = min_ps; + 2'd1: min_data = min_in; + endcase + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v new file mode 100644 index 000000000..5837d47e6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v @@ -0,0 +1,70 @@ +module FSM_second( + input wire rst, + input wire clk, + input wire [5:0] sec_in, + input wire sec_in_load, + output reg [5:0] sec_out); + + reg [2:0] ps, ns; + wire [5:0] sec_data_add; + reg [5:0] sec_data; + reg [5:0] sec_ps, sec_ns; + reg [1:0] sec_sel; + + always@(posedge clk) + begin + if(rst) ps <= 3'd0; + else ps <= ns; + end + + always@(posedge clk) + begin + if(rst) sec_ps <= 6'd0; + else sec_ps <= sec_ns; + end + + always@(*) + begin + sec_sel = 2'd0; + case(ps) + 3'd0: begin + ns = 3'd1; + end + 3'd1: begin + if(sec_in_load) begin + sec_sel = 2'd1; + sec_out = sec_data; + ns = 3'd2; + sec_ns = sec_data_add; + end + else ns = 3'd1; + end + 3'd2: begin + if(sec_data == 6'd59) begin + sec_out = sec_data; + ns = 3'd2; + sec_ns = 6'd0; + end + else begin + sec_out = sec_data; + ns = 3'd2; + sec_ns = sec_data_add; + end + end + default: begin + ns = 3'd0; + end + endcase + end + + assign sec_data_add = sec_data + 1; + + always@(*) + begin + case(sec_sel) + 2'd0: sec_data = sec_ps; + 2'd1: sec_data = sec_in; + endcase + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v new file mode 100644 index 000000000..f8e4f498d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v @@ -0,0 +1,34 @@ +module FSM_three_tb; + + reg rst; + reg clk; + reg [5:0] sec_in, min_in, hour_in; + reg load_in; + wire [5:0] sec_out, min_out, hour_out; + + FSM_top FSM_1( + .rst(rst), + .clk(clk), + .sec_in(sec_in), + .load_in(load_in), + .sec_out(sec_out), + .min_in(min_in), + .min_out(min_out), + .hour_in(hour_in), + .hour_out(hour_out)); + + initial begin + #0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5; + #100 rst = 1'd0; + #50 load_in = 1'd0; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #100000 $stop; + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v new file mode 100644 index 000000000..2587af165 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v @@ -0,0 +1,37 @@ +module FSM_top( + input wire rst, + input wire clk, + input wire load_in, + input wire [5:0] sec_in, + input wire [5:0] min_in, + input wire [5:0] hour_in, + output wire [5:0] sec_out, + output wire [5:0] min_out, + output wire [5:0] hour_out + ); + + FSM_second FSM_sec( + .rst(rst), + .clk(clk), + .sec_in(sec_in), + .sec_in_load(load_in), + .sec_out(sec_out)); + + FSM_minute FSM_min( + .rst(rst), + .clk(clk), + .min_in(min_in), + .min_in_load(load_in), + .sec_count(sec_out), + .min_out(min_out)); + + FSM_hour FSM_hr( + .rst(rst), + .clk(clk), + .hour_in(hour_in), + .hour_in_load(load_in), + .min_count(min_out), + .hour_out(hour_out), + .sec_count(sec_out)); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v new file mode 100644 index 000000000..798446a64 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v @@ -0,0 +1,27 @@ +module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code); + +output zero_flag_out; +output reg [7:0]alu_out; +input [7:0]Reg_Y_in,Bus_1_in; +input [7:0]IR_code; + +wire [3:0]opcode=IR_code[7:4]; + + + +always@(*) + begin + case(opcode) + 1: alu_out=Reg_Y_in+Bus_1_in; + 2: alu_out=Bus_1_in+~(Reg_Y_in)+1; + 3: alu_out=Reg_Y_in&(Bus_1_in); + 4: alu_out=~(Bus_1_in); + default:alu_out=8'b0; + endcase + end + +assign zero_flag_out=~|alu_out; + +endmodule + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v new file mode 100644 index 000000000..eae6c7ceb --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v @@ -0,0 +1,211 @@ +module Controller(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC, +Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,write, +zero,instruction,nclk,rst); + + +//狀態 +parameter S_idle=0,S_fet1=1,S_fet2=2,S_dec=3, + S_ex1=4,S_rd1=5,S_rd2=6,S_wr1=7,S_wr2=8, + S_br1=9,S_br2=10,S_halt=11; +//指令 +parameter NOP=0,ADD=1,SUB=2,AND=3,NOT=4, + RD=5,WR=6,BR=7,BRZ=8; + + +output reg L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC, + L_IR,L_ADD_R,L_R_Y,L_R_Z,write; +output reg[2:0]Sel_Bus1; +output reg [1:0]Sel_Bus2; + +input zero,nclk,rst; +input [7:0]instruction; + +reg [15:0]Con_out; +reg [3:0]PS,NS; +reg err_flag; + +wire [1:0]src=instruction[3:2]; +wire [1:0]dest=instruction[1:0]; +wire [3:0]opcode=instruction[7:4]; + +always@(posedge nclk) + begin + if(rst==1)PS<=0; + else PS<=NS; + end + +always@(PS,opcode,src,dest,zero) + begin + L_R0=0; + L_R1=0; + L_R2=0; + L_R3=0; + L_PC=0; + Inc_PC=0; + Sel_Bus1=0; + L_IR=0; + L_ADD_R=0; + L_R_Y=0; + L_R_Z=0; + Sel_Bus2=0; + write=0; + err_flag=0; + case(PS) + S_idle: NS=S_fet1; + + S_fet1: begin + NS=S_fet2; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=2'b01;//Sel_Bus1 + L_ADD_R=1; + end + + S_fet2: begin + NS=S_dec; + Sel_Bus2=2'b10;//Sel_Mem + L_IR=1; + Inc_PC=1; + end + + S_dec: begin + case(opcode) + NOP:NS=S_fet1; + ADD,SUB,AND:begin + NS=S_ex1; + Sel_Bus2=2'b01;//Sel_Bus1 + L_R_Y=1; + case(src) + 0: Sel_Bus1=3'b000;//R0 + 1: Sel_Bus1=3'b001;//R1 + 2: Sel_Bus1=3'b010;//R2 + 3: Sel_Bus1=3'b011;//R3 + default err_flag=1; + endcase + end//ADD,SUB,AND + + NOT:begin + NS=S_fet1; + L_R_Z=1; + Sel_Bus2=2'b00;//Sel_ALU + case(src) + 0: Sel_Bus1=3'b000;//R0 + 1: Sel_Bus1=3'b001;//R1 + 2: Sel_Bus1=3'b010;//R2 + 3: Sel_Bus1=3'b011;//R3 + default err_flag=1; + endcase + case(dest) + 0: L_R0=1; + 1: L_R1=1; + 2: L_R2=1; + 3: L_R3=1; + default err_flag=1; + endcase + end//NOT + + RD: begin + NS=S_rd1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end//RD + + WR: begin + NS=S_wr1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end//WR + + BR: begin + NS=S_br1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end//BR + + BRZ:begin + if(zero==1)begin + NS=S_br1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end + else begin + NS=S_fet1; + Inc_PC=1; + end + end//BRZ + + default NS=S_halt; + + endcase//opcode + end + + S_ex1: begin + NS=S_fet1; + L_R_Z=1; + Sel_Bus2=2'b00;//Sel_ALU + case(dest) + 0: begin Sel_Bus1=3'b000;L_R0=1;end + 1: begin Sel_Bus1=3'b001;L_R1=1;end + 2: begin Sel_Bus1=3'b010;L_R2=1;end + 3: begin Sel_Bus1=3'b011;L_R3=1;end + default err_flag=1; + endcase + end + + S_rd1: begin + NS=S_rd2; + Inc_PC=1; + Sel_Bus2=2'b10;//Sel_Mem + L_ADD_R=1; + end + + S_wr1: begin + NS=S_wr2; + Inc_PC=1; + Sel_Bus2=2'b10;//Sel_Mem + L_ADD_R=1; + end + + S_rd2: begin + NS=S_fet1; + Sel_Bus2=2'b10;//Sel_Mem + case(dest) + 0: L_R0=1; + 1: L_R1=1; + 2: L_R2=1; + 3: L_R3=1; + default err_flag=1; + endcase + end + + S_wr2: begin + NS=S_fet1; + write=1; + case(src) + 0: Sel_Bus1=3'b000;//R0 + 1: Sel_Bus1=3'b001;//R1 + 2: Sel_Bus1=3'b010;//R2 + 3: Sel_Bus1=3'b011;//R3 + default err_flag=1; + endcase + end + + S_br1: begin + NS=S_br2; + Sel_Bus2=2'b10;//Sel_Mem + L_ADD_R=1; + end + + S_br2: begin + NS=S_fet1; + Sel_Bus2=2'b10;//Sel_Mem + L_PC=1; + end + S_halt: NS=S_halt; + default NS=S_idle; + endcase + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v new file mode 100644 index 000000000..cdf41abfc --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v @@ -0,0 +1,13 @@ +module IR(IR_out,IR_in,load,clk,rst); + +output reg [7:0]IR_out; +input [7:0]IR_in; +input load,clk,rst; + +always@(posedge clk) + begin + if(rst==1)IR_out<=8'b0; + else if(load==1)IR_out<=IR_in; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v new file mode 100644 index 000000000..3f25916e2 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v @@ -0,0 +1,61 @@ +module Memory(Data_out,Address); + + output [7:0]Data_out; + input [7:0]Address; + + reg [7:0]mem[255:0]; + assign Data_out=mem[Address]; + + always@(Address) + begin + case(Address) + //opcode_src_dest + //NOP + 0: mem[Address]=8'b0000_00_00; + + //rd 00 10 //Read MEM[130] to R2 + 1: mem[Address]=8'b0101_00_10; //Instruction + 2: mem[Address]=130; //Address + + //rd 00 11 //Read MEM[131] to R3 + 3: mem[Address]=8'b0101_00_11; //Instruction + 4: mem[Address]=131; //Address + + //rd 00 01 //Read MEM[128] to R1 + 5: mem[Address]=8'b0101_00_01; //Instruction + 6: mem[Address]=128; //Address + + //rd 00 00 //Read MEM[129] to R0 + 7: mem[Address]=8'b0101_00_00; //Instruction + 8: mem[Address]=129; //Address + + //Sub 00 01 //Sub R1-R0 to R1 + 9: mem[Address]=8'b0010_00_01; //Instruction + + //BRZ 00 00 + 10: mem[Address]=8'b1000_00_00; //Instruction + 11: mem[Address]=134; //Address + + //Add 10 11 //Add R2+R3 to R3 + 12: mem[Address]=8'b00011011; + + //BR + 13: mem[Address]=8'b01110011; //Instruction + 14: mem[Address]=140; //Address + + 128:mem[Address]=6; + 129:mem[Address]=1; + 130:mem[Address]=2; + 131:mem[Address]=0; + 134:mem[Address]=139; //Address + 135:mem[Address]=0; + //HAL + 139:mem[Address]=8'b1111_00_00; //Instruction + 140:mem[Address]=9; //Address + default mem[Address]=8'bx; + endcase + end + +endmodule + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v new file mode 100644 index 000000000..1f678f02b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v @@ -0,0 +1,20 @@ +module Mux_31(Y,A0,A1,A2,sel); + +output [7:0]Y; +input [7:0]A2,A1,A0; +input [1:0]sel; + +reg [7:0]Y; + +always@(*) + begin + case(sel) + 0: Y=A0; + 1: Y=A1; + 2: Y=A2; + default:Y=8'bz; + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v new file mode 100644 index 000000000..213069454 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v @@ -0,0 +1,22 @@ +module Mux_51(Y,A0,A1,A2,A3,A4,sel); + +output [7:0]Y; +input [7:0]A4,A3,A2,A1,A0; +input [2:0]sel; + +reg [7:0]Y; + +always@(*) + begin + case(sel) + 0: Y=A0; + 1: Y=A1; + 2: Y=A2; + 3: Y=A3; + 4: Y=A4; + default:Y=8'bx; + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v new file mode 100644 index 000000000..f82c44e92 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v @@ -0,0 +1,17 @@ +module PC(PC_out,PC_in,load,inc,clk,rst); + +output [7:0]PC_out; +input [7:0]PC_in; +input load,inc,clk,rst; + +reg [7:0]PC_out; + +always@(posedge clk) + begin + if(rst==1)PC_out<=8'b0; + else if(load==1)PC_out<=PC_in; + else if(inc==1)PC_out<=PC_out+8'b00000001; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v new file mode 100644 index 000000000..910b52408 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v @@ -0,0 +1,23 @@ +module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst); + +output [7:0]bus_1_out; +input clk,rst; +output [7:0]Reg_R0_out; +output [7:0]Reg_R1_out; +output [7:0]Reg_R2_out; +output [7:0]Reg_R3_out; + +wire [7:0]bus_1_out,MEMAddress; +wire clk,rst; +wire [7:0]MEMdataout; +wire [7:0]Reg_R0_out; +wire [7:0]Reg_R1_out; +wire [7:0]Reg_R2_out; +wire [7:0]Reg_R3_out; + + +RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress); + +Memory MEM(MEMdataout,MEMAddress); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v new file mode 100644 index 000000000..a12b867b1 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v @@ -0,0 +1,48 @@ +module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress); + +output [7:0]bus_1_out,MEMAddress; +input clk,rst; +input [7:0]MEMdataout; +output [7:0]Reg_R0_out; +output [7:0]Reg_R1_out; +output [7:0]Reg_R2_out; +output [7:0]Reg_R3_out; + +wire [7:0]BUS_2,BUS_1,MEMAddress; +wire [7:0]alu_out; +wire [7:0]MEMdataout; +wire [7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out; +wire [7:0]IR_out; +wire zero_flag_out; +wire [2:0]Sel_Bus1; +wire [1:0]Sel_Bus2; +wire L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero; + +assign bus_1_out=BUS_1; +assign bus_2_out=BUS_2; + +Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst); +//module PC(PC_out,PC_in,load,inc,clk,rst); +PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst); +//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code); +ALU Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out); +//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite); +//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite); +//module Mux_31(Y,A0,A1,A2,sel); +Mux_31 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2); +//module Reg_1bit(Q,D,load,clk,rst); +Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst); +//module Reg_8bit(Q,D,load,clk,rst); +Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst); +Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst); +//R0~R3 +Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst); +Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst); +Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst); +Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst); +//module Mux_51(Y,A0,A1,A2,A3,A4,sel); +Mux_51 Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1); +//module IR(IR_out,IR_in,load,clk,rst); +IR Instruction_Register(IR_out,BUS_2,L_IR,clk,rst); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v new file mode 100644 index 000000000..371c84da3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v @@ -0,0 +1,53 @@ +`timescale 1ns/1ns + +module RISC_testbench; + +wire [7:0]bus_1_out; +reg clk,rst; +wire [7:0]Reg_R0_out; +wire [7:0]Reg_R1_out; +wire [7:0]Reg_R2_out; +wire [7:0]Reg_R3_out; + +/* wire [7:0]MEMAddress; +wire [7:0]MEMdataout; +wire MEMwrite; */ + +/* assign MEMAddress = top.MEMAddress; +assign MEMdataout = top.MEMdataout; +assign MEMwrite = top.MEMwrite; */ + +RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst); + + always#20 clk=~clk; + + initial + begin + clk=0;rst=1; + #30 rst=0; + #6000 $stop; + end + +/* //---------- + + integer fp; + initial + begin + fp = $fopen("RISC_xa.vec"); + + $fdisplay(fp, "radix 1 1 44 44 44 44 44 1 44 44"); + $fdisplay(fp, "vname clk rst Reg_R0_out[[7:0]] Reg_R1_out[[7:0]] Reg_R2_out[[7:0]] Reg_R3_out[[7:0]] bus_1_out[[7:0]] MEMwrite MEMAddress MEMdataout"); + $fdisplay(fp, " io i i oo oo oo oo oo o oo ii"); + $fdisplay(fp, "slope 0.3"); + $fdisplay(fp, " vih 3.3"); + $fdisplay(fp, " vil 0"); + $fdisplay(fp, "tunit ns"); + end + always@(clk) + begin + $fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout); + end + +//---------- */ + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v new file mode 100644 index 000000000..67bc59367 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v @@ -0,0 +1,16 @@ +module Reg_1bit(Q,D,load,clk,rst); + +output Q; +input D; +input load,clk,rst; + +reg Q; + +always@(posedge clk) + begin + if(rst==1)Q<=0; + else if(load==1)Q<=D; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v new file mode 100644 index 000000000..2b9bd810e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v @@ -0,0 +1,16 @@ +module Reg_8bit(Q,D,load,clk,rst); + +output [7:0]Q; +input [7:0]D; +input load,clk,rst; + +reg [7:0]Q; + +always@(posedge clk) + begin + if(rst==1)Q<=8'b0; + else if(load==1)Q<=D; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v new file mode 100644 index 000000000..acd178ea4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v @@ -0,0 +1,19 @@ +module ACC( + output [7:0] acc_out1, + output [7:0] acc_out2, + input [7:0] acc_in, + input la_, + input clk, + input clr_ + ); + + reg [7:0] q; + + always @(posedge clk) + if (~clr_) q <= 8'b0; + else if(~la_) q <= acc_in; + + assign acc_out1 = q; + assign acc_out2 = q; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v new file mode 100644 index 000000000..79719f59e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v @@ -0,0 +1,13 @@ +module ADDSUB( + output [7:0] ADDSUB_out, + input [7:0] ADDSUB_in1, + input [7:0] ADDSUB_in2, + input su + ); + + wire [7:0] d; + + assign d = su ? ADDSUB_in1 - ADDSUB_in2 : ADDSUB_in1 + ADDSUB_in2; + assign ADDSUB_out = d; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v new file mode 100644 index 000000000..e8ea08b2d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v @@ -0,0 +1,13 @@ +module BRegister( + output reg [7:0] BRegister_out, + input [7:0] BRegister_in, + input lb_, + input clk, + input clr_ + ); + + always @(posedge clk) + if(~clr_) BRegister_out <= 8'b0; + else if(~lb_) BRegister_out <= BRegister_in; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v new file mode 100644 index 000000000..5a14a8f4d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v @@ -0,0 +1,119 @@ +module Controller( + output reg [11:0] control_signals, + input [3:0] opcode, + input clk, + input clr_ + ); + + reg [3:0] ps, ns; + + always @(posedge clk) + begin + if(~clr_) ps <= 4'd0; + else ps <= ns; + end + + always @(*) + begin + case(ps) + 0: + begin + control_signals = 12'h3e3; + ns = 4'd1; + end + + 1: //T1 + begin + control_signals = 12'h5e3; + ns = 4'd2; + end + + 2: //T2 + begin +// control_signals = 12'hbe3; + control_signals = 12'h863; + ns = 4'd3; + end + + 3: //T3 + begin +// control_signals = 12'h263; + control_signals = 12'h3e3; + if(opcode == 4'd0) //LDA + ns = 4'd4; + else if(opcode == 4'd1) //ADD + ns = 4'd6; + else if(opcode == 4'd2) //SUB + ns = 4'd9; + else if(opcode == 4'd14) //OUT + ns = 4'd12; + else if(opcode == 4'd15) //HLT + ns = 4'd13; + end + + 4: //LDA + begin + control_signals = 12'h1a3; + ns = 4'd5; + end + + 5: //LDA + begin + control_signals = 12'h2c3; + ns = 4'd1; + end + + 6: //ADD + begin + control_signals = 12'h1a3; + ns = 4'd7; + end + + 7: //ADD + begin + control_signals = 12'h2e1; + ns = 4'd8; + end + + 8: //ADD + begin + control_signals = 12'h3c7; + ns = 4'd1; + end + + 9: //SUB + begin + control_signals = 12'h1a3; + ns = 4'd10; + end + + 10: //SUB + begin + control_signals = 12'h2e1; + ns = 4'd11; + end + + 11: //SUB + begin + control_signals = 12'h3cf; + ns = 4'd1; + end + + 12: //OUT + begin + control_signals = 12'h3f2; + ns = 4'd1; + end + + 13: //HLT + ns = 4'd13; + + default: + begin + ns = 4'd0; + control_signals = 12'h3e3; + end + + endcase + end +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v new file mode 100644 index 000000000..f95a31453 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v @@ -0,0 +1,21 @@ +module IR( + output [7:4] opcode, + output [3:0] oprand, + input wire [7:0] IR_in, + input li_, + input clk, + input clr_ + ); + + reg [7:0] q; + + always @(posedge clk) + begin + if(~clr_) q <=8'b0; + else if(~li_) q <= IR_in; + end + + assign opcode = q[7:4]; + assign oprand = q[3:0]; + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v new file mode 100644 index 000000000..0408bf01b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v @@ -0,0 +1,13 @@ +module MAR( + output reg [3:0] mar_out, + input wire [3:0] mar_in, + input lm_, + input clk, + input clr_ + ); + + always @(posedge clk) + if(~clr_) mar_out <= 4'b0; + else if(~lm_) mar_out <= mar_in; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v new file mode 100644 index 000000000..6bc7aac2a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v @@ -0,0 +1,13 @@ +module OutputRegister( + output reg [7:0] OutputRegister_out, + input [7:0] OutputRegister_in, + input lo_, + input clk, + input clr_ + ); + + always @(posedge clk) + if(~clr_) OutputRegister_out <= 8'b0; + else if(~lo_) OutputRegister_out <= OutputRegister_in; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v new file mode 100644 index 000000000..c987145e9 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v @@ -0,0 +1,15 @@ + module PC( + output reg [3:0] pc_out, + input cp, + input clk, + input clr_ + ); + + always @(posedge clk) + begin + if(~clr_) pc_out <= 0; + else if (cp) pc_out <= pc_out + 1; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v new file mode 100644 index 000000000..5fab7744b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v @@ -0,0 +1,26 @@ +module ROM( + output reg [7:0] rom_out, + input [3:0] rom_in + ); + + always @(*) + begin + rom_out = 8'bx; + case(rom_in) + 4'b0000: rom_out = 8'b0000_1001; //LDA + 4'b0001: rom_out = 8'b0001_1010; //ADD + 4'b0010: rom_out = 8'b0001_1011; //ADD + 4'b0011: rom_out = 8'b0010_1100; //SUB + 4'b0100: rom_out = 8'b1110_xxxx; //OUT + 4'b0101: rom_out = 8'b1111_xxxx; //HLT + 4'b0110: rom_out = 8'bxxxx_xxxx; + 4'b0111: rom_out = 8'bxxxx_xxxx; + 4'b1000: rom_out = 8'bxxxx_xxxx; + 4'b1001: rom_out = 8'b0001_0000; + 4'b1010: rom_out = 8'b0001_0100; + 4'b1011: rom_out = 8'b0001_1000; + 4'b1100: rom_out = 8'b0010_0000; + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v new file mode 100644 index 000000000..63d2513b7 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v @@ -0,0 +1,100 @@ +module SAPone( + output wire [7:0] SAP_out, + output wire [11:0] con, + output reg [7:0] bus, + input clk, + input clr_ + ); + + wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_; + wire [7:0] acc_out2, BRegister_out, OutputRegister_out; + wire [3:0] IR_out, mar_out; + wire [4:0] bus_sel; + wire [3:0] pc_out, oprand; + wire [7:0] rom_out, acc_out1, ADDSUB_out; + + assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con; + assign bus_sel = {ep, ce_, ei_, ea, eu}; + + always@(*) + begin + case(bus_sel) + 5'b11100: bus[3:0] = pc_out; + 5'b00100: bus[7:0] = rom_out; + 5'b01000: bus[3:0] = oprand; + 5'b01110: bus[7:0] = acc_out1; + 5'b01101: bus[7:0] = ADDSUB_out; + default: bus[7:0] = 8'bx; + endcase + end + + PC pc1( + .pc_out(pc_out), + .cp(cp), + .clk(clk), + .clr_(clr_) + ); + + MAR mar1( + .mar_out(mar_out), + .mar_in(bus[3:0]), + .lm_(lm_), + .clk(clk), + .clr_(clr_) + ); + + ROM roml( + .rom_out(rom_out), + .rom_in(mar_out) + ); + + IR ir1( + .opcode(IR_out), + .oprand(oprand), + .IR_in(bus[7:0]), + .li_(li_), + .clk(clk), + .clr_(clr_) + ); + + Controller cont1( + .control_signals(con), + .opcode(IR_out), + .clk(clk), + .clr_(clr_) + ); + + ACC acc1( + .acc_out1(acc_out1), + .acc_out2(acc_out2), + .acc_in(bus[7:0]), + .la_(la_), + .clk(clk), + .clr_(clr_) + ); + + ADDSUB addsub1( + .ADDSUB_out(ADDSUB_out), + .ADDSUB_in1(acc_out2), + .ADDSUB_in2(BRegister_out), + .su(su) + ); + + BRegister bregister1( + .BRegister_out(BRegister_out), + .BRegister_in(bus[7:0]), + .lb_(lb_), + .clk(clk), + .clr_(clr_) + ); + + OutputRegister outputregister1( + .OutputRegister_out(SAP_out), + .OutputRegister_in(bus[7:0]), + .lo_(lo_), + .clk(clk), + .clr_(clr_) + ); + + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v new file mode 100644 index 000000000..3f0b4e4dd --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v @@ -0,0 +1,34 @@ +module testSAPone; + + wire [7:0] SAP_out; + wire [11:0] con; + wire [7:0] bus; +// wire clk_out, clr_out; + reg clk, clr_; + + always #5 clk = ~clk; + + SAPone sapone1( + .SAP_out(SAP_out), + .con(con), + .bus(bus), +// .clk_out(clk_out), +// .clr_out(clr_out), + .clk(clk), + .clr_(clr_) + ); + +// PC pc1(bus[3:0], clk, clr_, cp, ep); +// MAR mar1(mar, clk, lm_, bus[3:0]); + + initial + begin + clk = 0; clr_ = 0; + #10 clr_ = 1; + + + + #990 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v new file mode 100644 index 000000000..216053285 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v @@ -0,0 +1,16 @@ +module counter(clk_counter, q_counter, rst_counter); + + input clk_counter; + input rst_counter; + output [7:0] q_counter; + reg [7:0] q_counter; + + always @ (posedge clk_counter) + begin + if(rst_counter) + q_counter <= 8'b00000000; + else + q_counter <= q_counter + 1; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v deleted file mode 100644 index 17896cc04..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v +++ /dev/null @@ -1,84 +0,0 @@ -/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */ - -module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] ); - wire _00_; - wire _01_; - input clk_counter; - wire n22; - wire n26; - wire n30; - wire n34; - wire n38; - wire n42; - wire n46; - wire n50; - output \q_counter[0] ; - reg \q_counter[0] ; - output \q_counter[1] ; - reg \q_counter[1] ; - output \q_counter[2] ; - reg \q_counter[2] ; - output \q_counter[3] ; - reg \q_counter[3] ; - output \q_counter[4] ; - reg \q_counter[4] ; - output \q_counter[5] ; - reg \q_counter[5] ; - output \q_counter[6] ; - reg \q_counter[6] ; - output \q_counter[7] ; - reg \q_counter[7] ; - input rst_counter; - - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[0] <= 1'b0; - else \q_counter[0] <= n22; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[1] <= 1'b0; - else \q_counter[1] <= n26; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[2] <= 1'b0; - else \q_counter[2] <= n30; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[3] <= 1'b0; - else \q_counter[3] <= n34; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[4] <= 1'b0; - else \q_counter[4] <= n38; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[5] <= 1'b0; - else \q_counter[5] <= n42; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[6] <= 1'b0; - else \q_counter[6] <= n46; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[7] <= 1'b0; - else \q_counter[7] <= n50; - end - - assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter }; - assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] }; - assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] }; - assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] }; - assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter }; - assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] }; - assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter }; - assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] }; - assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] }; - assign n22 = 4'h1 >> { \q_counter[0] , rst_counter }; -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif deleted file mode 100644 index ebf780381..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif +++ /dev/null @@ -1,69 +0,0 @@ -# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os) - -.model counter -.inputs clk_counter rst_counter -.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7] -.names $false -.names $true -1 -.names $undef -.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0] -0011 1 -1000 1 -1001 1 -1010 1 -.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_ -111111 1 -.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0] -010 1 -100 1 -.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0] -010 1 -100 1 -.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_ -11111 1 -.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0] -0011 1 -1000 1 -1001 1 -1010 1 -.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0] -001111 1 -100000 1 -100001 1 -100010 1 -100011 1 -100100 1 -100101 1 -100110 1 -100111 1 -101000 1 -101001 1 -101010 1 -101011 1 -101100 1 -101101 1 -101110 1 -.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0] -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0] -010 1 -100 1 -.names q_counter[0] rst_counter $0\q_counter[0][0:0] -00 1 -.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2 -.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2 -.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2 -.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2 -.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2 -.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2 -.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2 -.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2 -.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act deleted file mode 100644 index 800b2a89e..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act +++ /dev/null @@ -1,20 +0,0 @@ -clk_counter 0.500000 2.000000 -rst_counter 0.492200 0.201800 -q_counter[0] 0.281800 0.563400 -q_counter[1] 0.248200 0.273600 -q_counter[2] 0.183200 0.125600 -q_counter[3] 0.097400 0.044800 -q_counter[4] 0.022600 0.007200 -q_counter[5] 0.002200 0.000800 -q_counter[6] 0.000000 0.000000 -q_counter[7] 0.000000 0.000000 -$0\q_counter[7][0:0] 0 0 -$0\q_counter[6][0:0] 0 0 -$0\q_counter[5][0:0] 0 0 -$0\q_counter[4][0:0] 0 0 -$0\q_counter[3][0:0] 0 0 -$0\q_counter[2][0:0] 0 0 -$0\q_counter[1][0:0] 0 0 -$0\q_counter[0][0:0] 0 0 -$abc$3686$new_n23_ 0 0 -$abc$3686$new_n20_ 0 0 diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v new file mode 100644 index 000000000..accfd8267 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v @@ -0,0 +1,24 @@ +module counter_tb; + + reg clk_counter, rst_counter; + wire [7:0] q_counter; + + counter_original C_1( + clk_counter, + q_counter, + rst_counter); + + initial begin + #0 rst_counter = 1'b1; clk_counter = 1'b0; + #100 rst_counter = 1'b0; + end + + always begin + #10 clk_counter = ~clk_counter; + end + + initial begin + #5000 $stop; + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act new file mode 100644 index 000000000..43f1f55f1 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act @@ -0,0 +1,3 @@ +a 0.5 0.5 +b 0.5 0.5 +c 0.25 0.75 diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif new file mode 100644 index 000000000..941e6b51f --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif @@ -0,0 +1,8 @@ +.model or2 +.inputs a b +.outputs c + +.names a b c +00 0 + +.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v new file mode 100644 index 000000000..0f8dc04d9 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v @@ -0,0 +1,18 @@ +///////////////////////////////////////// +// Functionality: 2-input OR +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module or2( + a, + b, + c); + +input wire a; +input wire b; +output wire c; + +assign c = a | b; + +endmodule diff --git a/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml b/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml index 7d4840e56..81716fb00 100644 --- a/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml +++ b/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml @@ -1,35 +1,35 @@ - + - - + + - + - - + + - + - + - + - + - - + + diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index 0799af78e..2e5dede96 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -23,5 +23,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f - stdcell: If circuit designs are built with standard cells only - tree\_mux: If routing multiplexers are built with a tree-like structure - : The technology node which the delay numbers are extracted from. +- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating. Other features are used in naming should be listed here. diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml new file mode 100644 index 000000000..bf96e1aa0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -0,0 +1,206 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 0fa650846..7f31c435f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -242,7 +242,7 @@ - + @@ -277,7 +277,7 @@ - + @@ -310,7 +310,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml new file mode 100644 index 000000000..74d1d9933 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml new file mode 100644 index 000000000..721fb6663 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml new file mode 100644 index 000000000..da7c4b76b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -0,0 +1,223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml new file mode 100644 index 000000000..b39c7a999 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -0,0 +1,222 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/behavioral_verilog/config/task.conf index 88dcf68a2..0e1a11deb 100644 --- a/openfpga_flow/tasks/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/behavioral_verilog/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index a35635cf4..30e2367f7 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf index 4b731c716..7fa78a379 100644 --- a/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf index 3b3fa43b2..3da4d6263 100644 --- a/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/iverilog_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/iverilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml diff --git a/openfpga_flow/tasks/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/bram/dpram16k/config/task.conf index decb20187..a001231df 100644 --- a/openfpga_flow/tasks/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/bram/dpram16k/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf index 04cf52c9f..048f5e236 100644 --- a/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/compilation_verification/config/task.conf b/openfpga_flow/tasks/compilation_verification/config/task.conf index dca01bcfd..a8ae907f9 100644 --- a/openfpga_flow/tasks/compilation_verification/config/task.conf +++ b/openfpga_flow/tasks/compilation_verification/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/depopulate_crossbar/config/task.conf b/openfpga_flow/tasks/depopulate_crossbar/config/task.conf new file mode 100644 index 000000000..b6b8fa9c9 --- /dev/null +++ b/openfpga_flow/tasks/depopulate_crossbar/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf index 68079ff8c..650132a45 100644 --- a/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf +++ b/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf index a396bb03f..f465fe4fb 100644 --- a/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf index b0eba5ea8..08b46bef5 100644 --- a/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml diff --git a/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf index 0b026ac5c..a4737dbfe 100644 --- a/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml diff --git a/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf index 25cfc09ac..5e78d1462 100644 --- a/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf +++ b/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf index a1c85ee59..c5abfbf78 100644 --- a/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf +++ b/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf index 975cfd8f4..b6658090b 100644 --- a/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf +++ b/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf @@ -8,13 +8,15 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml diff --git a/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf index 333cb6d63..7b107698e 100644 --- a/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/flatten_routing/config/task.conf b/openfpga_flow/tasks/flatten_routing/config/task.conf index bcee2e245..7fdd7f456 100644 --- a/openfpga_flow/tasks/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/flatten_routing/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/config/task.conf new file mode 100644 index 000000000..eba6485e2 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/config/task.conf @@ -0,0 +1,32 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf new file mode 100644 index 000000000..4db289d23 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/generate_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf similarity index 94% rename from openfpga_flow/tasks/generate_bitstream/config/task.conf rename to openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf index e684dd543..aa4a6cb82 100644 --- a/openfpga_flow/tasks/generate_bitstream/config/task.conf +++ b/openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf index 9b21a6a26..cb1eb9a5c 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf @@ -8,29 +8,27 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf index dab7a9e3c..04342ba43 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf @@ -8,29 +8,27 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf index 8fabc7635..d0ab2bad6 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf @@ -14,23 +14,22 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf index 5ef4a8a2a..5c1eed83a 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf @@ -8,29 +8,27 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf index feb5f4372..bfa88b66e 100644 --- a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf @@ -8,29 +8,27 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf index 45946b434..00b210d8f 100644 --- a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf @@ -8,29 +8,27 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf index 94957ac84..6e48c7da7 100644 --- a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf @@ -8,29 +8,27 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/generate_fabric/config/task.conf b/openfpga_flow/tasks/generate_fabric/config/task.conf index 0da9d6248..9c3fd2442 100644 --- a/openfpga_flow/tasks/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/generate_fabric/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/generate_testbench/config/task.conf b/openfpga_flow/tasks/generate_testbench/config/task.conf index 011aa823c..f8c81bb1b 100644 --- a/openfpga_flow/tasks/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/generate_testbench/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/hard_adder/config/task.conf b/openfpga_flow/tasks/hard_adder/config/task.conf index 6f4efcd1e..0b3ecf486 100644 --- a/openfpga_flow/tasks/hard_adder/config/task.conf +++ b/openfpga_flow/tasks/hard_adder/config/task.conf @@ -8,13 +8,15 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/implicit_verilog/config/task.conf b/openfpga_flow/tasks/implicit_verilog/config/task.conf index 5ebdd49a7..e56a04fca 100644 --- a/openfpga_flow/tasks/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/implicit_verilog/config/task.conf @@ -8,27 +8,26 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v [SYNTHESIS_PARAM] bench0_top = counter -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/io/aib/config/task.conf b/openfpga_flow/tasks/io/aib/config/task.conf index 17367750a..68741ad1c 100644 --- a/openfpga_flow/tasks/io/aib/config/task.conf +++ b/openfpga_flow/tasks/io/aib/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= ##################################### # Debugging status diff --git a/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf index 96a4d348e..fb326c021 100644 --- a/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml diff --git a/openfpga_flow/tasks/io/reduced_io/config/task.conf b/openfpga_flow/tasks/io/reduced_io/config/task.conf index 50671bfd9..88b7b74c8 100644 --- a/openfpga_flow/tasks/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/io/reduced_io/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml diff --git a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf index 08a28be87..fbe91030d 100644 --- a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf @@ -8,19 +8,20 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] # diff --git a/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf index 7e8e55be9..35584d351 100644 --- a/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf +++ b/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/lut_design/single_mode/config/task.conf index 2f12d2377..7753da7cb 100644 --- a/openfpga_flow/tasks/lut_design/single_mode/config/task.conf +++ b/openfpga_flow/tasks/lut_design/single_mode/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index 620e575bc..72cb951d0 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml diff --git a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf index a9ddefc19..6ed171b79 100644 --- a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf @@ -8,19 +8,20 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf index 426bb8884..b6decc57b 100644 --- a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf @@ -8,19 +8,20 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf index 9c63bfdbd..0508a2181 100644 --- a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf @@ -8,19 +8,20 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/ncounter/config/task.conf b/openfpga_flow/tasks/ncounter/config/task.conf index 33ed59e53..75af20185 100644 --- a/openfpga_flow/tasks/ncounter/config/task.conf +++ b/openfpga_flow/tasks/ncounter/config/task.conf @@ -8,13 +8,15 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf b/openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf new file mode 100644 index 000000000..fe450ce38 --- /dev/null +++ b/openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf index 53354162b..e6c0caea0 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf @@ -8,27 +8,26 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf index dca01bcfd..ecf61f537 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf @@ -8,27 +8,26 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf index a413be671..5ce4abf20 100644 --- a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf @@ -8,27 +8,26 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf index bb9f7c11f..a99aa4e24 100644 --- a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf @@ -8,27 +8,26 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/sdc_time_unit/config/task.conf index c1d780690..102363652 100644 --- a/openfpga_flow/tasks/sdc_time_unit/config/task.conf +++ b/openfpga_flow/tasks/sdc_time_unit/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/spypad/config/task.conf b/openfpga_flow/tasks/spypad/config/task.conf index 51197d1f7..0d0bbb547 100644 --- a/openfpga_flow/tasks/spypad/config/task.conf +++ b/openfpga_flow/tasks/spypad/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml diff --git a/openfpga_flow/tasks/untileable/config/task.conf b/openfpga_flow/tasks/untileable/config/task.conf index cdc1769b1..13c0cdf62 100644 --- a/openfpga_flow/tasks/untileable/config/task.conf +++ b/openfpga_flow/tasks/untileable/config/task.conf @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml diff --git a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml new file mode 100644 index 000000000..a31984e8b --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +