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Pre-Merge modifications

This commit is contained in:
Baudouin Chauviere 2019-07-12 10:48:43 -06:00
parent a0f1f8d163 f0ecc51b51
commit f140e08093
2 changed files with 54 additions and 42 deletions
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12
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -736,7 +736,7 @@ t_block* search_mapped_block(int x, int y, int z) {
assert((0 < x)||(0 == x)); assert((0 < x)||(0 == x));
assert((x < (nx + 1))||(x == (nx + 1))); assert((x < (nx + 1))||(x == (nx + 1)));
assert((0 < y)||(0 == y)); assert((0 < y)||(0 == y));
assert((x < (ny + 1))||(x == (ny + 1))); assert((y < (ny + 1))||(y == (ny + 1)));
/* Search all blocks*/ /* Search all blocks*/
for (iblk = 0; iblk < num_blocks; iblk++) { for (iblk = 0; iblk < num_blocks; iblk++) {
@ -3479,10 +3479,10 @@ int my_strlen_int(int input_int) {
boolean my_bool_to_boolean(bool my_bool) { boolean my_bool_to_boolean(bool my_bool) {
if(true == my_bool) if(true == my_bool) {
return TRUE; return TRUE;
if(false == my_bool) } else {
return FALSE; assert (false == my_bool);
vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n"); return FALSE;
exit(1); }
} }

84
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -221,20 +221,27 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "`endif\n"); fprintf(fp, "`endif\n");
} }
/* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */
boolean subckt_require_explicit_port_map = FALSE;
if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) {
subckt_require_explicit_port_map = TRUE;
}
/* Call the subckt*/ /* Call the subckt*/
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
fprintf(fp, "\n"); fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model /* Only dump the global ports belonging to a spice_model
* Disable recursive here ! * Disable recursive here !
*/ */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
fprintf(fp, ",\n"); fprintf(fp, ",\n");
} }
/* assert */ /* assert */
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
/* print ports --> input ports */ /* print ports --> input ports */
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping)); dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE,
subckt_require_explicit_port_map);
/* IOPADs requires a specical port to output */ /* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) { if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n"); fprintf(fp, ",\n");
@ -248,7 +255,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* Print inout port */ /* Print inout port */
fprintf(fp, "%s%s[%d]", gio_inout_prefix, fprintf(fp, "%s%s[%d]", gio_inout_prefix,
verilog_model->prefix, verilog_model->cnt); verilog_model->prefix, verilog_model->cnt);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ", "); fprintf(fp, ", ");
@ -262,7 +269,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_SCAN_CHAIN: case SPICE_SRAM_SCAN_CHAIN:
/* Add explicit port mapping if required */ /* Add explicit port mapping if required */
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port); assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]); assert( NULL != sram_ports[0]);
fprintf(fp, ".%s (", fprintf(fp, ".%s (",
@ -272,7 +279,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1, cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT); 0, VERILOG_PORT_CONKT);
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (true == subckt_require_explicit_port_map)) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
@ -283,7 +290,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", "); fprintf(fp, ", ");
/* Add explicit port mapping if required */ /* Add explicit port mapping if required */
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port); assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]); assert( NULL != sram_ports[0]);
fprintf(fp, ".%s (", fprintf(fp, ".%s (",
@ -293,14 +300,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1, cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == verilog_model->dump_explicit_port_map || is_explicit_mapping)) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
break; break;
case SPICE_SRAM_MEMORY_BANK: case SPICE_SRAM_MEMORY_BANK:
/* Add explicit port mapping if required */ /* Add explicit port mapping if required */
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port); assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]); assert( NULL != sram_ports[0]);
fprintf(fp, ".%s (", fprintf(fp, ".%s (",
@ -310,7 +317,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1, cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT); 0, VERILOG_PORT_CONKT);
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == subckt_require_explicit_port_map)) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
/* Check if we have an inverterd prefix */ /* Check if we have an inverterd prefix */
@ -320,7 +327,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", "); fprintf(fp, ", ");
/* Add explicit port mapping if required */ /* Add explicit port mapping if required */
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port); assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]); assert( NULL != sram_ports[0]);
fprintf(fp, ".%s (", fprintf(fp, ".%s (",
@ -330,7 +337,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1, cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
if ( (0 < num_sram) if ( (0 < num_sram)
&& (true == is_explicit_mapping)) { && (TRUE == subckt_require_explicit_port_map)) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
break; break;
@ -593,6 +600,11 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
/* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */
boolean subckt_require_explicit_port_map = FALSE;
if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) {
subckt_require_explicit_port_map = TRUE;
}
/* Call LUT subckt*/ /* Call LUT subckt*/
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
fprintf(fp, "\n"); fprintf(fp, "\n");
@ -601,13 +613,13 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
* Only dump the global ports belonging to a spice_model * Only dump the global ports belonging to a spice_model
* DISABLE recursive here ! * DISABLE recursive here !
*/ */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
fprintf(fp, ",\n"); fprintf(fp, ",\n");
} }
/* Connect inputs*/ /* Connect inputs*/
/* Connect outputs*/ /* Connect outputs*/
fprintf(fp, "//----- Input and output ports -----\n"); fprintf(fp, "//----- Input and output ports -----\n");
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping)); dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, subckt_require_explicit_port_map);
fprintf(fp, "\n//----- SRAM ports -----\n"); fprintf(fp, "\n//----- SRAM ports -----\n");
/* check */ /* check */
@ -619,88 +631,88 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_STANDALONE: case SPICE_SRAM_STANDALONE:
break; break;
case SPICE_SRAM_SCAN_CHAIN: case SPICE_SRAM_SCAN_CHAIN:
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_out( "); fprintf(fp, ".sram_out( ");
} }
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1, cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT); 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ", "); fprintf(fp, ", ");
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_outb( "); fprintf(fp, ".sram_outb( ");
} }
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1, cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
if (0 < num_mode_sram) { if (0 < num_mode_sram) {
fprintf(fp, ", "); fprintf(fp, ", ");
if (true == is_explicit_mapping) { }
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_out( "); fprintf(fp, ".mode_out( ");
} }
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT); 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ", "); fprintf(fp, ", ");
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_outb( "); fprintf(fp, ".mode_outb( ");
} }
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
}
break; break;
case SPICE_SRAM_MEMORY_BANK: case SPICE_SRAM_MEMORY_BANK:
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_out( "); fprintf(fp, ".sram_out( ");
} }
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1, cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT); 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ", "); fprintf(fp, ", ");
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_outb( "); fprintf(fp, ".sram_outb( ");
} }
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1, cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
if (0 < num_mode_sram) { if (0 < num_mode_sram) {
fprintf(fp, ", "); fprintf(fp, ", ");
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_out( "); fprintf(fp, ".mode_out( ");
} }
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT); 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ", "); fprintf(fp, ", ");
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_outb( "); fprintf(fp, ".mode_outb( ");
} }
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
} }
if (true == is_explicit_mapping) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
break; break;