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deploy single mode in regression tests

This commit is contained in:
tangxifan 2020-04-20 13:16:52 -06:00
parent 489ca75230
commit f06f2d72be
1 changed files with 3 additions and 0 deletions
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.travis/script.sh
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@ -51,6 +51,9 @@ echo -e "Testing OpenFPGA Shell";
echo -e "Testing configuration chain of a K4N4 FPGA"; echo -e "Testing configuration chain of a K4N4 FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
echo -e "Testing Verilog generation for a single mode LUT6 FPGA using micro benchmarks";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/single_mode --debug --show_thread_logs
echo -e "Testing Verilog generation with simple fracturable LUT6 "; echo -e "Testing Verilog generation with simple fracturable LUT6 ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs