Travis Experiments Squashed
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parent
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commit
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@ -45,3 +45,4 @@ tmp/
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build/
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message.txt
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deploy_key
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66
.travis.yml
66
.travis.yml
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@ -1,35 +1,22 @@
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language: cpp
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# cache results
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cache:
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directories:
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- $TRAVIS_BUILD_DIR/abc
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- $TRAVIS_BUILD_DIR/yosys
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- $TRAVIS_BUILD_DIR/ace2
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- $TRAVIS_BUILD_DIR/libs
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- $HOME/.ccache
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- $HOME/deps
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# Currently sudo is not required, NO ENV is used
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# Supported Operating systems
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#os:
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# - linux
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# - osx
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# Create a matrix to branch the building environment
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- "$TRAVIS_BUILD_DIR/abc"
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- "$TRAVIS_BUILD_DIR/yosys"
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- "$TRAVIS_BUILD_DIR/ace2"
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- "$TRAVIS_BUILD_DIR/libs"
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- "$HOME/.ccache"
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- "$HOME/deps"
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matrix:
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include:
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- os: linux
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# Compiler is specified in ./travis/common.sh
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sudo: false
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dist: bionic
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compiler: g++-8
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addons:
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apt:
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sources:
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- ubuntu-toolchain-r-test # For newer GCC
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- george-edison55-precise-backports # For cmake
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- sourceline: ppa:ubuntu-toolchain-r/test
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packages:
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- autoconf
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- automake
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@ -63,29 +50,16 @@ matrix:
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- valgrind
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- zip
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- qt5-default
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# - os: osx
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# osx_image: xcode10.2 # we target latest MacOS Mojave
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# sudo: true
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# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
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# addons:
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# homebrew:
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# packages:
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# - bison
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# - cmake
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# - ctags
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# - flex
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# - fontconfig
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# - git
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# - gcc@6
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# - gcc@4.9
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# - gawk
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# - icarus-verilog
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# - libxml++
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# - qt5
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before_install:
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- openssl aes-256-cbc -K $encrypted_6f6cf68308be_key -iv $encrypted_6f6cf68308be_iv -in deploy_key.enc -out ./deploy_key -d
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- eval "$(ssh-agent -s)"
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- chmod 600 ./deploy_key
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- echo -e "Host $SERVER_IP_ADDRESS\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
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- ssh-add ./deploy_key
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- ssh -o StrictHostKeyChecking=no -i ./deploy_key u1249762@lab1-1.eng.utah.edu pwd
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- echo $TRAVIS_JOB_ID >> build_id.txt
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- scp -o StrictHostKeyChecking=no -i ./deploy_key build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/build_id.txt
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- source .travis/common.sh
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install:
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- DEPS_DIR="${HOME}/deps"
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- mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
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@ -101,16 +75,12 @@ install:
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- cmake --version
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- cd -
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- source .travis/install.sh
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script:
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- .travis/script.sh
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#- .travis/regression.sh
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- ".travis/script.sh"
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after_failure:
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- .travis/after_failure.sh
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- ".travis/after_failure.sh"
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after_success:
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- .travis/after_success.sh
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- ".travis/after_success.sh"
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notifications:
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slack:
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secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=
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@ -19,19 +19,19 @@ end_section "OpenFPGA.build"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd -
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echo -e "Testing single-mode architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug
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python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
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#python3 openfpga_flow/scripts/run_fpga_task.py s298
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# echo -e "Testing multi-mode architectures";
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# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
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echo -e "Testing multi-mode architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
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# echo -e "Testing compact routing techniques";
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# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
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echo -e "Testing compact routing techniques";
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python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
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# echo -e "Testing tileable architectures";
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# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
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echo -e "Testing tileable architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
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# echo -e "Testing Verilog generation with explicit port mapping ";
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# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
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echo -e "Testing Verilog generation with explicit port mapping ";
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python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
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end_section "OpenFPGA.TaskTun"
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