Travis Experiments Squashed

This commit is contained in:
Ganesh Gore 2019-11-01 23:26:31 -06:00
parent 94b60b9714
commit f042c35edf
4 changed files with 84 additions and 113 deletions

1
.gitignore vendored
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@ -45,3 +45,4 @@ tmp/
build/
message.txt
deploy_key

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@ -1,35 +1,22 @@
language: cpp
# cache results
cache:
directories:
- $TRAVIS_BUILD_DIR/abc
- $TRAVIS_BUILD_DIR/yosys
- $TRAVIS_BUILD_DIR/ace2
- $TRAVIS_BUILD_DIR/libs
- $HOME/.ccache
- $HOME/deps
# Currently sudo is not required, NO ENV is used
# Supported Operating systems
#os:
# - linux
# - osx
# Create a matrix to branch the building environment
- "$TRAVIS_BUILD_DIR/abc"
- "$TRAVIS_BUILD_DIR/yosys"
- "$TRAVIS_BUILD_DIR/ace2"
- "$TRAVIS_BUILD_DIR/libs"
- "$HOME/.ccache"
- "$HOME/deps"
matrix:
include:
- os: linux
# Compiler is specified in ./travis/common.sh
sudo: false
dist: bionic
compiler: g++-8
addons:
apt:
sources:
- ubuntu-toolchain-r-test # For newer GCC
- george-edison55-precise-backports # For cmake
- sourceline: ppa:ubuntu-toolchain-r/test
packages:
- autoconf
- automake
@ -63,29 +50,16 @@ matrix:
- valgrind
- zip
- qt5-default
# - os: osx
# osx_image: xcode10.2 # we target latest MacOS Mojave
# sudo: true
# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
# addons:
# homebrew:
# packages:
# - bison
# - cmake
# - ctags
# - flex
# - fontconfig
# - git
# - gcc@6
# - gcc@4.9
# - gawk
# - icarus-verilog
# - libxml++
# - qt5
before_install:
- openssl aes-256-cbc -K $encrypted_6f6cf68308be_key -iv $encrypted_6f6cf68308be_iv -in deploy_key.enc -out ./deploy_key -d
- eval "$(ssh-agent -s)"
- chmod 600 ./deploy_key
- echo -e "Host $SERVER_IP_ADDRESS\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
- ssh-add ./deploy_key
- ssh -o StrictHostKeyChecking=no -i ./deploy_key u1249762@lab1-1.eng.utah.edu pwd
- echo $TRAVIS_JOB_ID >> build_id.txt
- scp -o StrictHostKeyChecking=no -i ./deploy_key build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/build_id.txt
- source .travis/common.sh
install:
- DEPS_DIR="${HOME}/deps"
- mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
@ -101,16 +75,12 @@ install:
- cmake --version
- cd -
- source .travis/install.sh
script:
- .travis/script.sh
#- .travis/regression.sh
- ".travis/script.sh"
after_failure:
- .travis/after_failure.sh
- ".travis/after_failure.sh"
after_success:
- .travis/after_success.sh
- ".travis/after_success.sh"
notifications:
slack:
secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=

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@ -19,19 +19,19 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py s298
# echo -e "Testing multi-mode architectures";
# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
# echo -e "Testing compact routing techniques";
# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
# echo -e "Testing tileable architectures";
# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
# echo -e "Testing Verilog generation with explicit port mapping ";
# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
end_section "OpenFPGA.TaskTun"

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