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try to fix the bug in clock net identification

This commit is contained in:
tangxifan 2019-08-13 16:47:28 -06:00
parent 1118b28397
commit edfa72a666
3 changed files with 7 additions and 5 deletions
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5
vpr7_x2p/vpr/SRC/base/read_blif.c
View File

@ -524,7 +524,7 @@ static void add_latch(int doall, INP t_model *latch_model) {
/* Store the initial value */
logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]);
/* Add clock identification */
logical_block[logical_block[num_logical_blocks - 1].clock_net].is_clock = TRUE;
logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE;
/*END*/
num_latches++;
@ -722,6 +722,9 @@ static void add_subckt(int doall, t_model *user_models) {
add_vpack_net(circuit_signal_name[i], RECEIVER,
num_logical_blocks - 1, port->index,
my_atoi(pin_number), TRUE, doall);
/* Add clock identification */
logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE;
} else {
logical_block[num_logical_blocks - 1].input_nets[port->index][my_atoi(
pin_number)] = add_vpack_net(

6
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
View File

@ -1005,8 +1005,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,
cur_pb_type->physical_mode_num_conf_bits = 0;
/* Recursively finish all the child pb_types*/
if ((NULL == cur_pb_type->spice_model_name)
&& (NULL == cur_pb_type->physical_pb_type_name)) {
if ( FALSE == is_primitive_pb_type(cur_pb_type)) {
/* Find the mode that define_idle_mode*/
mode_index = find_pb_type_physical_mode_index((*cur_pb_type));
for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) {
@ -1017,8 +1016,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,
}
/* Check if this has defined a spice_model*/
if ((NULL != cur_pb_type->spice_model_name)
|| (NULL != cur_pb_type->physical_pb_type_name)) {
if ( TRUE == is_primitive_pb_type(cur_pb_type)) {
sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, cur_sram_orgz_info->type, 0);
cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits;
/* calculate the number of reserved configuration bits */

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -1751,6 +1751,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* update stamped sram counter */
stamped_sram_cnt += cur_pb_type->physical_mode_num_conf_bits;
/* Check */
if (stamped_sram_cnt != get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info))
assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info));
assert(stamped_iopad_cnt == iopad_verilog_model->cnt);
/* Finish for primitive node, return */