From edfa72a666731a9423b55782490880a0564a60d7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 13 Aug 2019 16:47:28 -0600
Subject: [PATCH] try to fix the bug in clock net identification

---
 vpr7_x2p/vpr/SRC/base/read_blif.c                       | 5 ++++-
 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 6 ++----
 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c     | 1 +
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/vpr7_x2p/vpr/SRC/base/read_blif.c b/vpr7_x2p/vpr/SRC/base/read_blif.c
index 8e982725d..75008fc3f 100644
--- a/vpr7_x2p/vpr/SRC/base/read_blif.c
+++ b/vpr7_x2p/vpr/SRC/base/read_blif.c
@@ -524,7 +524,7 @@ static void add_latch(int doall, INP t_model *latch_model) {
     /* Store the initial value */
     logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]);
     /* Add clock identification */
-    logical_block[logical_block[num_logical_blocks - 1].clock_net].is_clock = TRUE;
+    logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE;
     /*END*/
 
 	num_latches++;
@@ -722,6 +722,9 @@ static void add_subckt(int doall, t_model *user_models) {
 								add_vpack_net(circuit_signal_name[i], RECEIVER,
 										num_logical_blocks - 1, port->index,
 										my_atoi(pin_number), TRUE, doall);
+
+                        /* Add clock identification */
+                        logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE;
 					} else {
 						logical_block[num_logical_blocks - 1].input_nets[port->index][my_atoi(
 								pin_number)] = add_vpack_net(
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
index 7e9042806..ca1f0a96a 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
@@ -1005,8 +1005,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,
   cur_pb_type->physical_mode_num_conf_bits = 0;
 
   /* Recursively finish all the child pb_types*/
-  if ((NULL == cur_pb_type->spice_model_name) 
-     && (NULL == cur_pb_type->physical_pb_type_name)) { 
+  if ( FALSE == is_primitive_pb_type(cur_pb_type)) {
     /* Find the mode that define_idle_mode*/
     mode_index = find_pb_type_physical_mode_index((*cur_pb_type));
     for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) {
@@ -1017,8 +1016,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,
   }
 
   /* Check if this has defined a spice_model*/
-  if ((NULL != cur_pb_type->spice_model_name)
-     || (NULL != cur_pb_type->physical_pb_type_name)) { 
+  if ( TRUE == is_primitive_pb_type(cur_pb_type)) {
     sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, cur_sram_orgz_info->type, 0);
     cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits;
     /* calculate the number of reserved configuration bits */
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
index 5db74a44f..f87ff45a7 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
@@ -1751,6 +1751,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
     /* update stamped sram counter */
     stamped_sram_cnt += cur_pb_type->physical_mode_num_conf_bits;
     /* Check */
+    if (stamped_sram_cnt != get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)) 
     assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); 
     assert(stamped_iopad_cnt == iopad_verilog_model->cnt);
     /* Finish for primitive node, return  */