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[Tool] Bug fix

This commit is contained in:
tangxifan 2021-07-02 15:32:30 -06:00
parent fdf94cba83
commit e9d29e27e5
2 changed files with 2 additions and 1 deletions
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1
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -157,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::vector<std::string>(),
std::string(FPGA_PORT_POSTFIX),
atom_ctx, netlist_annotation,
PinConstraints(),
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));

2
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -106,7 +106,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
* while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted)
* However, to ensure correct stimuli to the benchmark, we have to invert the signal
*/
if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
fp << "~";
}
fp << block_name;