From e9d29e27e50d49269f515c2298312093d987092c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:32:30 -0600 Subject: [PATCH] [Tool] Bug fix --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 1 + openfpga/src/fpga_verilog/verilog_testbench_utils.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index d27baccbd..47fc6a13d 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -157,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, + PinConstraints(), explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 01cdb0a22..3542cdcfc 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -106,7 +106,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) * However, to ensure correct stimuli to the benchmark, we have to invert the signal */ - if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { fp << "~"; } fp << block_name;