optimizing the constant writing in Verilog for single bits

2020-06-29 12:29:25 -06:00 · 2020-06-29 12:29:25 -06:00 · e9937954f2
parent 933801cfa7
commit e9937954f2
1 changed files with 4 additions and 0 deletions
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@ -661,6 +661,10 @@ std::string generate_verilog_constant_values(const std::vector<size_t>& const_va
    }
  }

+  if (1 == const_values.size()) {
+    same_values = false;
+  }
+
  std::string str;

  if ( (true == short_constant)