From e9937954f2e748b17f1e162d1096826c94c5c277 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 29 Jun 2020 12:29:25 -0600
Subject: [PATCH] optimizing the constant writing in Verilog for single bits

---
 openfpga/src/fpga_verilog/verilog_writer_utils.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 900c3da37..2817ccbaf 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -661,6 +661,10 @@ std::string generate_verilog_constant_values(const std::vector<size_t>& const_va
     }
   }
 
+  if (1 == const_values.size()) {
+    same_values = false;
+  }
+
   std::string str;
 
   if ( (true == short_constant)