Merge remote-tracking branch 'origin/master' into ganesh_dev

.github/workflows/build.yml

@@ -151,8 +151,8 @@ jobs:
             build/openfpga/libopenfpga.a
             build/openfpga/openfpga_shell.so
             build/openfpga/openfpga
-            yosys/install/share
+            build/yosys/share
-            yosys/install/bin
+            build/yosys/bin
             openfpga_flow
             openfpga.sh
 
@@ -446,11 +446,11 @@ jobs:
           chmod +x build/vtr-verilog-to-routing/ace2/ace
           chmod +x build/vtr-verilog-to-routing/vpr/vpr
           chmod +x build/openfpga/openfpga
-          chmod +x yosys/install/bin/yosys
+          chmod +x build/yosys/bin/yosys
-          chmod +x yosys/install/bin/yosys-abc
+          chmod +x build/yosys/bin/yosys-abc
-          chmod +x yosys/install/bin/yosys-config
+          chmod +x build/yosys/bin/yosys-config
-          chmod +x yosys/install/bin/yosys-filterlib
+          chmod +x build/yosys/bin/yosys-filterlib
-          chmod +x yosys/install/bin/yosys-smtbmc
+          chmod +x build/yosys/bin/yosys-smtbmc
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04)
         shell: bash
         run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs

CMakeLists.txt

@@ -312,14 +312,14 @@ endif()
 
 # we will check if yosys already exist. if not then build it
 if (OPENFPGA_WITH_YOSYS)
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys)
+    if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys/bin/yosys)
         message(STATUS "Yosys pre-build exist so skipping it")
     else ()
         # run makefile provided, we pass-on the options to the local make file 
         add_custom_target(
             yosys ALL 
             COMMAND $(MAKE) config-gcc
-            COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
+            COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys/
             WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys
             COMMENT "Compile Yosys with given Makefile"
         )
@@ -329,9 +329,9 @@ if (OPENFPGA_WITH_YOSYS)
         if (OPENFPGA_WITH_YOSYS_PLUGIN)
             add_custom_target(
                 yosys-plugins ALL
-                COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql"
+                COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_BINARY_DIR}/yosys EXTRA_FLAGS="-DPASS_NAME=synth_ql"
                 WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins
-                DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys
+                DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys/bin/yosys
                 COMMENT "Compile Yosys-plugins with given Makefile"
             )
             add_dependencies(yosys-plugins yosys)

Dockerfile

@@ -1,13 +1,32 @@
-FROM ghcr.io/lnis-uofu/openfpga-master:latest
+FROM ghcr.io/lnis-uofu/openfpga-master:8d555772
 
 # Install node js
-RUN curl -sL https://deb.nodesource.com/setup_12.x | bash -
+USER root
+RUN curl -sL https://deb.nodesource.com/setup_14.x | bash -
 RUN curl -fsSL https://code-server.dev/install.sh | sh
 RUN apt-get install -y nodejs
 RUN apt-get install tree
-RUN code-server --install-extension ms-python.python
 
-ARG NB_USER=openfpga_user
+# = = = = = = = VSCODE Extension installation = = = = = = =
+# Python support in vscode
+RUN code-server --install-extension ms-python.python
+# For CSV file alignment
+RUN code-server --install-extension mechatroner.rainbow-csv
+# For VCD Viewer
+RUN wget -O _wavetrace.gz https://marketplace.visualstudio.com/_apis/public/gallery/publishers/wavetrace/vsextensions/wavetrace/1.1.2/vspackage
+RUN code-server --install-extension wavetrace.wavetrace
+# For XML Linting
+RUN code-server --install-extension dotjoshjohnson.xml
+# For git graphs
+RUN code-server --install-extension mhutchie.git-graph
+# verilog-linter
+RUN code-server --install-extension mshr-h.veriloghdl
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+RUN usermod -u 2000 openfpga_user
+RUN groupmod -g 2000 openfpga_user
+
+ARG NB_USER=user_openfpga
 ARG NB_UID=1000
 ENV USER ${NB_USER}
 ENV NB_UID ${NB_UID}
@@ -18,23 +37,26 @@ RUN adduser --disabled-password \
     --uid ${NB_UID} \
     ${NB_USER}
 
-USER root
 RUN chown -R ${NB_UID} ${HOME}
 RUN chown -R ${NB_UID} /opt/openfpga
+
+WORKDIR ${HOME}
 USER ${NB_USER}
 
 ENV PATH $PATH:/home/${NB_USER}/.local/bin
 
+RUN python3 -m pip install --upgrade pip
 RUN python3 -m pip install --user --no-cache-dir notebook
 RUN python3 -m pip install --user --no-cache-dir jupyterlab
 RUN python3 -m pip install --user --no-cache-dir jupyterhub
+RUN python3 -m pip install --user --no-cache-dir "jupyter-server<2.0.0"
 RUN python3 -m pip install --user --no-cache-dir jupyter-server-proxy
 RUN python3 -m pip install --user --no-cache-dir jupyter-vscode-proxy
 
 RUN npm install @jupyterlab/server-proxy
 RUN jupyter serverextension enable --py jupyter_server_proxy
-RUN jupyter labextension install @jupyterlab/server-proxy
 RUN jupyter lab build
+WORKDIR /opt/openfpga/
 RUN git reset --hard HEAD
 
 # Set up terminal

VERSION.md

@@ -1 +1 @@
-1.2.672
+1.2.759

docker/Dockerfile.master

@@ -3,8 +3,8 @@ RUN mkdir -p /opt/openfpga
 WORKDIR /opt/openfpga
 COPY . /opt/openfpga
 RUN chmod +x build/vtr-verilog-to-routing/abc/abc build/vtr-verilog-to-routing/ace2/ace build/openfpga/openfpga build/vtr-verilog-to-routing/vpr/vpr
-RUN chmod +x yosys/install/bin/yosys yosys/install/bin/yosys-abc yosys/install/bin/yosys-config yosys/install/bin/yosys-filterlib yosys/install/bin/yosys-smtbmc
+RUN chmod +x build/yosys/bin/yosys build/yosys/bin/yosys-abc build/yosys/bin/yosys-config build/yosys/bin/yosys-filterlib build/yosys/bin/yosys-smtbmc
-ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/yosys/install/bin:${PATH}"
+ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/build/yosys/bin:${PATH}"
 ENV PATH="/opt/openfpga/build/vtr-verilog-to-routing/ace2:/opt/openfpga/build/vtr-verilog-to-routing/abc:/opt/openfpga/build/vtr-verilog-to-routing/vpr:${PATH}"
 ENV OPENFPGA_PATH="/opt/openfpga"
 

docs/source/conf.py

@@ -185,7 +185,7 @@ texinfo_documents = [
 ]
 
 
-bibtex_bibfiles = ["z_reference.bib"]
+bibtex_bibfiles = ["./appendix/z_reference.bib"]
 
 # -- Options for Epub output -------------------------------------------------
 
@@ -203,3 +203,22 @@ epub_title = project
 
 # A list of files that should not be packed into the epub file.
 epub_exclude_files = ['search.html']
+
+# ========
+# Headings
+# ========
+#
+# Headings
+# ========
+#
+# Heading 3
+# ---------
+#
+# Heading 4
+# ^^^^^^^^^
+#
+# Heading 5
+# ~~~~~~~~~
+#
+# Heading 6
+# *********

docs/source/manual/arch_lang/circuit_model_examples.rst

@@ -523,9 +523,9 @@ Template
 
 .. option:: <design_technology type="<string>" structure="<string>" num_level="<int>" add_const_input="<bool>" const_input_val="<int>" local_encoder="<bool>"/>
 
-  - ``structure="tree|multi-level|one-level"`` Specify the multiplexer structure for a multiplexer. The structure option is only valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the one-level structure
+  - ``structure="tree|multi_level|one_level"`` Specify the multiplexer structure for a multiplexer. The structure option is only valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the one_level structure
 
-  - ``num_level="<int>"`` Specify the number of levels when ``multi-level`` structure is selected.
+  - ``num_level="<int>"`` Specify the number of levels when ``multi_level`` structure is selected.
     
   - ``add_const_input="true|false"`` Specify if an extra input should be added to the multiplexer circuits. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``.
 
@@ -563,7 +563,7 @@ The code describing this Multiplexer is:
 .. code-block:: xml
 
   <circuit_model type="mux" name="mux_1level" prefix="mux_1level">
-    <design_technology type="cmos" structure="one-level"/>
+    <design_technology type="cmos" structure="one_level"/>
     <input_buffer exist="on" circuit_model_name="inv1x"/> 
     <output_buffer exist="on" circuit_model_name="tapbuf4"/> 
     <pass_gate_logic circuit_model_name="tgate"/>

docs/source/tutorials/getting_started/shell_shortcuts.rst

@@ -1,17 +1,18 @@
-OpenFPGA shortcuts
+OpenFPGA Shell Commands
-------------------
+-----------------------
 
-OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh``
+OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh``,
 
 .. code-block:: bash
 
+   export OPENFPGA_PATH=<path-to-openfpga-repository-root>
    cd ${OPENFPGA_PATH} && source openfpga.sh
 
 .. note::
     The OpenFPGA shortcut works with only a bash-like shell. e.g., `bash`/`zsh`/`fish,` etc.
 
-Shortcut Commands
+Commands
-^^^^^^^^^^^^^^^^^
+^^^^^^^^
 
 Once the ``openfpga.sh`` script is sourced, you can run any following commands directly in the terminal.
 
@@ -38,13 +39,21 @@ Once the ``openfpga.sh`` script is sourced, you can run any following commands d
    for example  ``create-task _my_task_copy basic_tests/generate_fabric`` create a copy of the ``basic_tests/generate_fabric`` task in
    the current directory with  ``_my_task_copy`` name.
 
-.. option:: run-modelsim
+.. option:: goto_task <task_name> <run_num[default 0]>
+
+   This command navigate shell to specific run-directory of the given task.
+   For example `goto_task lab1 2` will change directory to `run002` runt directory of `lab2`
+
+.. option:: clear-task-run <task_name>
+
+   Clears all run diretories of the given task
+
+.. option:: run-modelsim <task_name>
 
    This command runs the verification using ModelSim.
    The test benches are generated during the OpenFPGA run.
    **Note**: users need to have ``VSIM`` installed and configured
 
-
 .. option:: run-regression-local
 
    This script runs the regression test locally using the current version of OpenFPGA.

openfpga.sh

@@ -42,8 +42,9 @@ create-task () {
     fi
     template="template_tasks/yosys_vpr_template"
     if [ ${#2} -ge 1 ]; then
-        if   [[ "$2" == "vpr_blif" ]]; then template="template_tasks/${2}_template/";
+        if   [[ "$2" == "fabric_netlist_gen" ]]; then template="template_tasks/${2}_template/";
-        elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/"; 
+        elif [[ "$2" == "fabric_verification" ]]; then template="template_tasks/${2}_template/";
+        elif [[ "$2" == "frac-lut-arch-explore" ]]; then template="template_tasks/${2}_template/";
         elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/";
         else template="$2"
         fi
@@ -57,6 +58,11 @@ create-task () {
     cp -r $OPENFPGA_PATH/openfpga_flow/tasks/${template}/* $1/
 }
 
+rerun-task () {
+    $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all
+    $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
+}
+
 run-task () {
     $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
 }

openfpga_flow/misc/fpgaflow_default_tool_path.conf

@@ -1,13 +1,13 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
 openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
-yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
+yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
-abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
+abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys-abc
 abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
-abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
+abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
-vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
+vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr
 ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace
 pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
 iverilog_path = iverilog

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -203,8 +203,9 @@ run-task basic_tests/io_constraints/empty_pcf $@
 run-task basic_tests/io_constraints/pcf_ql_style $@
 
 echo -e "Testing project templates";
-run-task template_tasks/vpr_blif_template $@
+run-task template_tasks/fabric_netlist_gen_template $@
-run-task template_tasks/yosys_vpr_template $@
+run-task template_tasks/fabric_verification_template $@
+run-task template_tasks/frac-lut-arch-explore_template $@
 run-task template_tasks/vtr_benchmarks_template $@
 
 echo -e "Testing create tsk from template and run task"

openfpga_flow/scripts/run_fpga_task.py

@@ -67,7 +67,9 @@ parser.add_argument(
 )
 parser.add_argument("--config", help="Override default configuration")
 parser.add_argument(
-    "--test_run", action="store_true", help="Dummy run shows final generated VPR commands"
+    "--test_run",
+    action="store_true",
+    help="Dummy run shows final generated VPR commands",
 )
 parser.add_argument("--debug", action="store_true", help="Run script in debug mode")
 parser.add_argument("--continue_on_fail", action="store_true", help="Exit script with return code")
@@ -83,10 +85,13 @@ task_script_dir = os.path.dirname(os.path.abspath(__file__))
 script_env_vars = {
     "PATH": {
         "OPENFPGA_FLOW_PATH": task_script_dir,
-        "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
+        "VPR_ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "vpr_arch"),
-        "OPENFPGA_SHELLSCRIPT_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "OpenFPGAShellScripts"),
+        "OF_ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "openfpga_arch"),
-        "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
+        "OPENFPGA_SHELLSCRIPT_PATH": os.path.join(
-        "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
+            "${PATH:OPENFPGA_PATH}", "openfpga_flow", "OpenFPGAShellScripts"
+        ),
+        "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "benchmarks"),
+        "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "tech"),
         "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
         "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
         "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir)),
@@ -381,8 +386,8 @@ def generate_each_task_actions(taskname):
     # architecture, benchmark and parameters
     # Create run_job object [arch, bench, run_dir, commnad]
     flow_run_cmd_list = []
-    for indx, arch in enumerate(archfile_list):
     for bench in benchmark_list:
+        for indx, arch in enumerate(archfile_list):
             for lbl, param in bench["script_params"].items():
                 if benchmark_top_module_count.count(bench["top_module"]) > 1:
                     flow_run_dir = get_flow_rundir(
@@ -400,6 +405,7 @@ def generate_each_task_actions(taskname):
                     param=param,
                     task_conf=task_conf,
                 )
+                command += ["--flow_config", curr_task_conf_file]
                 flow_run_cmd_list.append(
                     {
                         "arch": arch,
@@ -506,13 +512,21 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
 
     if args.debug:
         command += ["--debug"]
+
     return command
 
 
 def strip_child_logger_info(line):
     try:
         logtype, message = line.split(" - ", 1)
-        lognumb = {"CRITICAL": 50, "ERROR": 40, "WARNING": 30, "INFO": 20, "DEBUG": 10, "NOTSET": 0}
+        lognumb = {
+            "CRITICAL": 50,
+            "ERROR": 40,
+            "WARNING": 30,
+            "INFO": 20,
+            "DEBUG": 10,
+            "NOTSET": 0,
+        }
         logger.log(lognumb[logtype.strip().upper()], message)
     except:
         logger.info(line)
@@ -572,7 +586,9 @@ def run_actions(job_list):
     thread_list = []
     for _, eachjob in enumerate(job_list):
         t = threading.Thread(
-            target=run_single_script, name=eachjob["name"], args=(thread_sema, eachjob, job_list)
+            target=run_single_script,
+            name=eachjob["name"],
+            args=(thread_sema, eachjob, job_list),
         )
         t.start()
         thread_list.append(t)
@@ -581,6 +597,9 @@ def run_actions(job_list):
 
 
 def collect_results(job_run_list):
+    """
+    Collect performance numbers from vpr_stat.result file
+    """
     task_result = []
     for run in job_run_list:
         if not run["status"]:
@@ -588,25 +607,34 @@ def collect_results(job_run_list):
             continue
         # Check if any result file exist
         if not glob.glob(os.path.join(run["run_dir"], "*.result")):
-            logger.info("No result files found for %s" % run["name"])
+            logger.info("No result files found for %s", run["name"])
+            continue
 
         # Read and merge result file
         vpr_res = ConfigParser(allow_no_value=True, interpolation=ExtendedInterpolation())
-        vpr_res.read_file(open(os.path.join(run["run_dir"], "vpr_stat.result")))
+        vpr_result_file = os.path.join(run["run_dir"], "vpr_stat.result")
+        vpr_res.read_file(open(vpr_result_file, encoding="UTF-8"))
         result = OrderedDict()
         result["name"] = run["name"]
         result["TotalRunTime"] = int(run["endtime"] - run["starttime"])
         result.update(vpr_res["RESULTS"])
         task_result.append(result)
+
     colnames = []
-        for eachLbl in task_result:
+    # Extract all column names
-            colnames.extend(eachLbl.keys())
+    for each_metric in task_result:
-    if len(task_result):
+        colnames.extend(set(each_metric.keys()) - {"name", "TotalRunTime"})
-        with open("task_result.csv", "w", newline="") as csvfile:
+        colnames = sorted(list(set(colnames)))
-            writer = csv.DictWriter(csvfile, extrasaction="ignore", fieldnames=list(colnames))
+    if len(task_result) > 0:
+        with open("task_result.csv", "w", encoding="UTF-8", newline="") as csvfile:
+            writer = csv.DictWriter(
+                csvfile,
+                extrasaction="ignore",
+                fieldnames=["name", "TotalRunTime"] + colnames,
+            )
             writer.writeheader()
-            for eachResult in task_result:
+            for each in task_result:
-                writer.writerow(eachResult)
+                writer.writerow(each)
 
 
 if __name__ == "__main__":

openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/openfpga_arch.xml

@@ -1,11 +1,3 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-  -->
 <openfpga_architecture>
     <technology_library>
         <device_library>
@@ -157,21 +149,18 @@
         <segment name="L4" circuit_model_name="chan_segment"/>
     </routing_segment>
     <pb_type_annotations>
-        <!-- physical pb_type binding in complex block IO -->
+        <pb_type name="clb">
+            <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+        </pb_type>
+        <pb_type name="clb.fle" physical_mode_name="physical"/>
+        <pb_type name="clb.fle[physical].ble6.lut6" circuit_model_name="lut6"/>
+        <pb_type name="clb.fle[physical].ble6.ff" circuit_model_name="DFFSRQ"/>
+        <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].ble6.lut6"/>
+        <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].ble6.ff"/>
+
         <pb_type name="io" physical_mode_name="physical"/>
         <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
         <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
         <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
-        <!-- End physical pb_type binding in complex block IO -->
-
-        <!-- physical pb_type binding in complex block CLB -->
-        <!-- physical mode will be the default mode if not specified -->
-        <pb_type name="clb">
-            <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-            <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-        </pb_type>
-        <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
-        <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/>
-        <!-- End physical pb_type binding in complex block IO -->
     </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/vpr_arch.xml

@@ -0,0 +1,226 @@
+<?xml version="1.0" ?>
+<architecture>
+   <models>
+      <model name="io">
+         <input_ports>
+            <port name="outpad"/>
+         </input_ports>
+         <output_ports>
+            <port name="inpad"/>
+         </output_ports>
+      </model>
+   </models>
+   <tiles>
+      <tile name="io" area="0">
+         <sub_tile name="io" capacity="8">
+            <equivalent_sites>
+               <site pb_type="io"/>
+            </equivalent_sites>
+            <input name="outpad" num_pins="1"/>
+            <output name="inpad" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+            <pinlocations pattern="custom">
+               <loc side="left">io.outpad io.inpad</loc>
+               <loc side="top">io.outpad io.inpad</loc>
+               <loc side="right">io.outpad io.inpad</loc>
+               <loc side="bottom">io.outpad io.inpad</loc>
+            </pinlocations>
+         </sub_tile>
+      </tile>
+      <tile name="clb" area="53894">
+         <sub_tile name="clb">
+            <equivalent_sites>
+               <site pb_type="clb"/>
+            </equivalent_sites>
+            <input name="I" num_pins="40" equivalent="full"/>
+            <output name="O" num_pins="20" equivalent="none"/>
+            <clock name="clk" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+            <pinlocations pattern="spread"/>
+         </sub_tile>
+      </tile>
+   </tiles>
+   <!-- Physical descriptions begin -->
+   <layout tileable="true">
+      <auto_layout aspect_ratio="1.0">
+         <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+         <perimeter type="io" priority="100"/>
+         <corners type="EMPTY" priority="101"/>
+         <!--Fill with 'clb'-->
+         <fill type="clb" priority="10"/>
+      </auto_layout>
+   </layout>
+   <device>
+      <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+      <area grid_logic_tile_area="0"/>
+      <chan_width_distr>
+         <x distr="uniform" peak="1.000000"/>
+         <y distr="uniform" peak="1.000000"/>
+      </chan_width_distr>
+      <switch_block type="wilton" fs="3"/>
+      <connection_block input_switch_name="ipin_cblock"/>
+   </device>
+   <switchlist>
+      <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+      <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+   </switchlist>
+   <segmentlist>
+      <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+         <mux name="0"/>
+         <sb type="pattern">1 1 1 1 1</sb>
+         <cb type="pattern">1 1 1 1</cb>
+      </segment>
+   </segmentlist>
+   <complexblocklist>
+      <pb_type name="io">
+         <input name="outpad" num_pins="1"/>
+         <output name="inpad" num_pins="1"/>
+         <mode name="physical" disable_packing="true">
+            <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="iopad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+               </direct>
+               <direct name="inpad" input="iopad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="inpad">
+            <pb_type name="inpad" blif_model=".input" num_pb="1">
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="inpad" input="inpad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="outpad">
+            <pb_type name="outpad" blif_model=".output" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="outpad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <power method="ignore"/>
+      </pb_type>
+      <pb_type name="clb">
+         <input name="I" num_pins="40" equivalent="full"/>
+         <output name="O" num_pins="20" equivalent="none"/>
+         <clock name="clk" num_pins="1"/>
+         <pb_type name="fle" num_pb="10">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+             <!-- physical mode -->
+            <mode name="physical" disable_packing="true">
+               <!-- Define 6-LUT mode -->
+               <pb_type name="ble6" num_pb="1">
+                  <input name="in" num_pins="6"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Define LUT -->
+                  <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+                     <input name="in" num_pins="6" port_class="lut_in"/>
+                     <output name="out" num_pins="1" port_class="lut_out"/>
+                     <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                     </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                     <input name="D" num_pins="1" port_class="D"/>
+                     <output name="Q" num_pins="1" port_class="Q"/>
+                     <clock name="clk" num_pins="1" port_class="clock"/>
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                     <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+                     <direct name="direct2" input="lut6.out" output="ff.D">
+                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+                     </direct>
+                     <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+                     <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+                     </mux>
+                  </interconnect>
+               </pb_type>
+               <interconnect>
+                  <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+                  <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+                  <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+               </interconnect>
+            </mode>
+            <!-- end of physical mode -->
+            <!-- 6-LUT mode definition begin -->
+            <mode name="n1_lut6">
+               <!-- Define 6-LUT mode -->
+               <pb_type name="ble6" num_pb="1">
+                  <input name="in" num_pins="6"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Define LUT -->
+                  <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+                     <input name="in" num_pins="6" port_class="lut_in"/>
+                     <output name="out" num_pins="1" port_class="lut_out"/>
+                     <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                     </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                     <input name="D" num_pins="1" port_class="D"/>
+                     <output name="Q" num_pins="1" port_class="Q"/>
+                     <clock name="clk" num_pins="1" port_class="clock"/>
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                     <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+                     <direct name="direct2" input="lut6.out" output="ff.D">
+                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+                     </direct>
+                     <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+                     <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+                     </mux>
+                  </interconnect>
+               </pb_type>
+               <interconnect>
+                  <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+                  <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+                  <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+               </interconnect>
+            </mode>
+            <!-- n1_lut6 -->
+         </pb_type>
+         <interconnect>
+            <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+               <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+               <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+            </complete>
+            <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+            </complete>
+            <direct name="clbouts1" input="fle[9:0].out" output="clb.O[9:0]"/>
+         </interconnect>
+      </pb_type>
+   </complexblocklist>
+</architecture>

openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml

@@ -0,0 +1,192 @@
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="--1--"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="64"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/vpr_arch.xml

@@ -0,0 +1,191 @@
+<?xml version="1.0" ?>
+<architecture>
+   <models>
+      <!-- A virtual model for I/O to be used in the physical mode of io block -->
+      <model name="io">
+         <input_ports>
+            <port name="outpad"/>
+         </input_ports>
+         <output_ports>
+            <port name="inpad"/>
+         </output_ports>
+      </model>
+   </models>
+   <tiles>
+      <tile name="io" area="0">
+         <sub_tile name="io" capacity="8">
+            <equivalent_sites>
+               <site pb_type="io"/>
+            </equivalent_sites>
+            <input name="outpad" num_pins="1"/>
+            <output name="inpad" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+            <pinlocations pattern="custom">
+               <loc side="left">io.outpad io.inpad</loc>
+               <loc side="top">io.outpad io.inpad</loc>
+               <loc side="right">io.outpad io.inpad</loc>
+               <loc side="bottom">io.outpad io.inpad</loc>
+            </pinlocations>
+         </sub_tile>
+      </tile>
+      <tile name="clb" area="53894">
+         <sub_tile name="clb">
+            <equivalent_sites>
+               <site pb_type="clb"/>
+            </equivalent_sites>
+            <input name="I" num_pins="40" equivalent="full"/>
+            <output name="O" num_pins="10" equivalent="none"/>
+            <clock name="clk" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+            <pinlocations pattern="spread"/>
+         </sub_tile>
+      </tile>
+   </tiles>
+   <!-- ODIN II specific config ends -->
+   <!-- Physical descriptions begin -->
+   <layout tileable="true">
+      <auto_layout aspect_ratio="1.0">
+         <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+         <perimeter type="io" priority="100"/>
+         <corners type="EMPTY" priority="101"/>
+         <!--Fill with 'clb'-->
+         <fill type="clb" priority="10"/>
+      </auto_layout>
+   </layout>
+   <device>
+      <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+      <area grid_logic_tile_area="0"/>
+      <chan_width_distr>
+         <x distr="uniform" peak="1.000000"/>
+         <y distr="uniform" peak="1.000000"/>
+      </chan_width_distr>
+      <switch_block type="wilton" fs="3"/>
+      <connection_block input_switch_name="ipin_cblock"/>
+   </device>
+   <switchlist>
+      <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+      <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+   </switchlist>
+   <segmentlist>
+      <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+         <mux name="0"/>
+         <sb type="pattern">1 1 1 1 1</sb>
+         <cb type="pattern">1 1 1 1</cb>
+      </segment>
+   </segmentlist>
+   <complexblocklist>
+      <pb_type name="io">
+         <input name="outpad" num_pins="1"/>
+         <output name="inpad" num_pins="1"/>
+         <mode name="physical" disable_packing="true">
+            <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="iopad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+               </direct>
+               <direct name="inpad" input="iopad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="inpad">
+            <pb_type name="inpad" blif_model=".input" num_pb="1">
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="inpad" input="inpad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="outpad">
+            <pb_type name="outpad" blif_model=".output" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="outpad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+         <!-- IOs go on the periphery of the FPGA, for consistency,
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+         <!-- Place I/Os on the sides of the FPGA -->
+         <power method="ignore"/>
+      </pb_type>
+      <pb_type name="clb">
+         <input name="I" num_pins="40" equivalent="full"/>
+         <output name="O" num_pins="10" equivalent="none"/>
+         <clock name="clk" num_pins="1"/>
+         <pb_type name="fle" num_pb="10">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- 6-LUT mode definition begin -->
+            <mode name="n1_lut6">
+               <!-- Define 6-LUT mode -->
+               <pb_type name="ble6" num_pb="1">
+                  <input name="in" num_pins="6"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Define LUT -->
+                  <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+                     <input name="in" num_pins="6" port_class="lut_in"/>
+                     <output name="out" num_pins="1" port_class="lut_out"/>
+                     <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                        261e-12
+                        261e-12
+                        261e-12
+                        261e-12
+                        261e-12
+                        261e-12
+                     </delay_matrix>
+                  </pb_type>
+                  <!-- Define flip-flop -->
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                     <input name="D" num_pins="1" port_class="D"/>
+                     <output name="Q" num_pins="1" port_class="Q"/>
+                     <clock name="clk" num_pins="1" port_class="clock"/>
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                     <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+                     <direct name="direct2" input="lut6.out" output="ff.D">
+                        <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+                     </direct>
+                     <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+                     <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                        <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+                     </mux>
+                  </interconnect>
+               </pb_type>
+               <interconnect>
+                  <direct name="direct1" input="fle.in" output="ble6.in"/>
+                  <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+                  <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+               </interconnect>
+            </mode>
+            <!-- 6-LUT mode definition end -->
+         </pb_type>
+         <interconnect>
+            <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+               <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+               <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+            </complete>
+            <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+            </complete>
+            <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
+         </interconnect>
+      </pb_type>
+   </complexblocklist>
+</architecture>

openfpga_flow/tasks/template_tasks/fabric_verification_template/config/task.conf

@@ -13,25 +13,29 @@ power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
-# fpga_flow= vpr_blif If input in in .blif format
+fpga_flow=yosys_vpr
-# fpga_flow= yosys_vpr If input in in .v format
-fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:TASK_DIR}/example_script.openfpga
 openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
 
 [BENCHMARKS]
-bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.blif
+bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.v
+bench1=${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v
 
 [SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
+
 bench0_top = and2
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and2/and2.v
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1_top = mult8
+bench1_verilog = ${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga

@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@@ -44,6 +44,7 @@ build_fabric_bitstream --verbose
 
 # Write fabric-dependent bitstream
 write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
@@ -59,16 +60,6 @@ write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VE
 write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
 write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
 
-# Write the SDC files for PnR backend
-#  - Turn on every options here
-write_pnr_sdc --file ./SDC
-
-# Write SDC to disable timing for configure ports
-write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./SDC_analysis
-
 # Finish and exit OpenFPGA
 exit
 

openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/mult8/mult8.v

@@ -0,0 +1,22 @@
+//-------------------------------------------------------
+//  Functionality: A 8-bit combinational multiply circuit
+//-------------------------------------------------------
+
+module mult8(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
+			b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7,
+			out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
+			out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15);
+input a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7;
+input b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7;
+output out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
+output out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15;
+
+ assign a = {a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7};
+ assign b = {b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7};
+ assign out = {out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15};
+
+ assign out = a*b;
+
+endmodule
+
+

openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf

@@ -0,0 +1,49 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:TASK_DIR}/vtr_benchmark_template_script.openfpga
+openfpga_arch_file=${PATH:TASK_DIR}/openfpga_arch.xml
+vpr_route_chan_width=300
+
+[ARCHITECTURES]
+arch0=${PATH:TASK_DIR}/k6_N10_tileable.xml
+arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable.xml
+
+[BENCHMARKS]
+bench1=${PATH:BENCH_PATH}/vtr_benchmark/ch_intrinsics.v
+bench2=${PATH:BENCH_PATH}/vtr_benchmark/diffeq1.v
+bench3=${PATH:BENCH_PATH}/vtr_benchmark/diffeq2.v
+bench4=${PATH:BENCH_PATH}/vtr_benchmark/sha.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
+
+# Benchmark top_module name
+bench1_top = memset
+bench2_top = diffeq_paj_convert
+bench3_top = diffeq_f_systemC
+bench4_top = sha1
+
+[SCRIPT_PARAM_]
+#
+
+[DEFAULT_PARSE_RESULT_VPR]
+01_lut6_use = "lut6    : ([0-9]+)", int
+02_lut5_use = "lut5    : ([0-9]+)", int

openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml

@@ -0,0 +1,198 @@
+<?xml version="1.0" ?>
+<architecture>
+   <models>
+      <model name="io">
+         <input_ports>
+            <port name="outpad"/>
+         </input_ports>
+         <output_ports>
+            <port name="inpad"/>
+         </output_ports>
+      </model>
+   </models>
+   <tiles>
+      <tile name="io" area="0">
+         <sub_tile name="io" capacity="8">
+            <equivalent_sites>
+               <site pb_type="io"/>
+            </equivalent_sites>
+            <input name="outpad" num_pins="1"/>
+            <output name="inpad" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+            <pinlocations pattern="custom">
+               <loc side="left">io.outpad io.inpad</loc>
+               <loc side="top">io.outpad io.inpad</loc>
+               <loc side="right">io.outpad io.inpad</loc>
+               <loc side="bottom">io.outpad io.inpad</loc>
+            </pinlocations>
+         </sub_tile>
+      </tile>
+      <tile name="clb" area="53894">
+         <sub_tile name="clb">
+            <equivalent_sites>
+               <site pb_type="clb"/>
+            </equivalent_sites>
+            <input name="I" num_pins="40" equivalent="full"/>
+            <input name="cin" num_pins="1"/>
+            <output name="O" num_pins="20" equivalent="none"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+               <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+               <fc_override port_name="cout" fc_type="frac" fc_val="0" />
+            </fc>
+            <pinlocations pattern="custom">
+               <loc side="left">clb.clk</loc>
+               <loc side="top">clb.cin</loc>
+               <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+               <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+            </pinlocations>
+         </sub_tile>
+      </tile>
+   </tiles>
+   <!-- ODIN II specific config ends -->
+   <!-- Physical descriptions begin -->
+   <layout tileable="true" through_channel="false">
+      <auto_layout aspect_ratio="1.0">
+         <perimeter type="io" priority="100"/>
+         <corners type="EMPTY" priority="101"/>
+         <fill type="clb" priority="10"/>
+         <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      </auto_layout>
+      <fixed_layout name="3x2" width="5" height="4">
+         <perimeter type="io" priority="100"/>
+         <corners type="EMPTY" priority="101"/>
+         <fill type="clb" priority="10"/>
+         <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      </fixed_layout>
+   </layout>
+   <device>
+      <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+      <area grid_logic_tile_area="0"/>
+      <chan_width_distr>
+         <x distr="uniform" peak="1.000000"/>
+         <y distr="uniform" peak="1.000000"/>
+      </chan_width_distr>
+      <switch_block type="wilton" fs="3"/>
+      <connection_block input_switch_name="ipin_cblock"/>
+   </device>
+   <switchlist>
+      <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+      <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+   </switchlist>
+   <segmentlist>
+      <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+         <mux name="0"/>
+         <sb type="pattern">1 1 1 1 1</sb>
+         <cb type="pattern">1 1 1 1</cb>
+      </segment>
+   </segmentlist>
+   <complexblocklist>
+      <pb_type name="io">
+         <input name="outpad" num_pins="1"/>
+         <output name="inpad" num_pins="1"/>
+         <mode name="physical" disable_packing="true">
+            <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="iopad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+               </direct>
+               <direct name="inpad" input="iopad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="inpad">
+            <pb_type name="inpad" blif_model=".input" num_pb="1">
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="inpad" input="inpad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="outpad">
+            <pb_type name="outpad" blif_model=".output" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="outpad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <power method="ignore"/>
+      </pb_type>
+      <pb_type name="clb">
+         <input name="I" num_pins="40" equivalent="full"/>
+         <input name="cin" num_pins="1"/>
+         <output name="O" num_pins="20" equivalent="none"/>
+         <output name="cout" num_pins="1"/>
+         <clock name="clk" num_pins="1"/>
+         <pb_type name="fle" num_pb="10">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <mode name="n1_lut6">
+               <pb_type name="ble6" num_pb="1">
+                  <input name="in" num_pins="6"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+                     <input name="in" num_pins="6" port_class="lut_in"/>
+                     <output name="out" num_pins="1" port_class="lut_out"/>
+                     <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                     </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                     <input name="D" num_pins="1" port_class="D"/>
+                     <output name="Q" num_pins="1" port_class="Q"/>
+                     <clock name="clk" num_pins="1" port_class="clock"/>
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                     <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+                     <direct name="direct2" input="lut6.out" output="ff.D">
+                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+                     </direct>
+                     <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+                     <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+                     </mux>
+                  </interconnect>
+               </pb_type>
+               <interconnect>
+                  <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+                  <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+                  <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+               </interconnect>
+            </mode>
+            <!-- n1_lut6 -->
+         </pb_type>
+         <interconnect>
+            <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+               <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+               <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+            </complete>
+            <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+            </complete>
+            <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+            <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+         </interconnect>
+      </pb_type>
+   </complexblocklist>
+</architecture>

openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml

@@ -0,0 +1,245 @@
+<?xml version="1.0" ?>
+<architecture>
+   <models>
+      <model name="io">
+         <input_ports>
+            <port name="outpad"/>
+         </input_ports>
+         <output_ports>
+            <port name="inpad"/>
+         </output_ports>
+      </model>
+   </models>
+   <tiles>
+      <tile name="io" area="0">
+         <sub_tile name="io" capacity="8">
+            <equivalent_sites>
+               <site pb_type="io"/>
+            </equivalent_sites>
+            <input name="outpad" num_pins="1"/>
+            <output name="inpad" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+            <pinlocations pattern="custom">
+               <loc side="left">io.outpad io.inpad</loc>
+               <loc side="top">io.outpad io.inpad</loc>
+               <loc side="right">io.outpad io.inpad</loc>
+               <loc side="bottom">io.outpad io.inpad</loc>
+            </pinlocations>
+         </sub_tile>
+      </tile>
+      <tile name="clb" area="53894">
+         <sub_tile name="clb">
+            <equivalent_sites>
+               <site pb_type="clb"/>
+            </equivalent_sites>
+            <input name="I" num_pins="40" equivalent="full"/>
+            <input name="cin" num_pins="1"/>
+            <output name="O" num_pins="20" equivalent="none"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+               <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+               <fc_override port_name="cout" fc_type="frac" fc_val="0" />
+            </fc>
+            <pinlocations pattern="custom">
+               <loc side="left">clb.clk</loc>
+               <loc side="top">clb.cin</loc>
+               <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+               <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+            </pinlocations>
+         </sub_tile>
+      </tile>
+   </tiles>
+   <!-- ODIN II specific config ends -->
+   <!-- Physical descriptions begin -->
+   <layout tileable="true" through_channel="false">
+      <auto_layout aspect_ratio="1.0">
+         <perimeter type="io" priority="100"/>
+         <corners type="EMPTY" priority="101"/>
+         <fill type="clb" priority="10"/>
+         <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      </auto_layout>
+      <fixed_layout name="3x2" width="5" height="4">
+         <perimeter type="io" priority="100"/>
+         <corners type="EMPTY" priority="101"/>
+         <fill type="clb" priority="10"/>
+         <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      </fixed_layout>
+   </layout>
+   <device>
+      <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+      <area grid_logic_tile_area="0"/>
+      <chan_width_distr>
+         <x distr="uniform" peak="1.000000"/>
+         <y distr="uniform" peak="1.000000"/>
+      </chan_width_distr>
+      <switch_block type="wilton" fs="3"/>
+      <connection_block input_switch_name="ipin_cblock"/>
+   </device>
+   <switchlist>
+      <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+      <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+   </switchlist>
+   <segmentlist>
+      <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+         <mux name="0"/>
+         <sb type="pattern">1 1 1 1 1</sb>
+         <cb type="pattern">1 1 1 1</cb>
+      </segment>
+   </segmentlist>
+   <complexblocklist>
+      <pb_type name="io">
+         <input name="outpad" num_pins="1"/>
+         <output name="inpad" num_pins="1"/>
+         <mode name="physical" disable_packing="true">
+            <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="iopad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+               </direct>
+               <direct name="inpad" input="iopad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="inpad">
+            <pb_type name="inpad" blif_model=".input" num_pb="1">
+               <output name="inpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="inpad" input="inpad.inpad" output="io.inpad">
+                  <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <mode name="outpad">
+            <pb_type name="outpad" blif_model=".output" num_pb="1">
+               <input name="outpad" num_pins="1"/>
+            </pb_type>
+            <interconnect>
+               <direct name="outpad" input="io.outpad" output="outpad.outpad">
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+               </direct>
+            </interconnect>
+         </mode>
+         <power method="ignore"/>
+      </pb_type>
+      <pb_type name="clb">
+         <input name="I" num_pins="40" equivalent="full"/>
+         <input name="cin" num_pins="1"/>
+         <output name="O" num_pins="20" equivalent="none"/>
+         <output name="cout" num_pins="1"/>
+         <clock name="clk" num_pins="1"/>
+         <pb_type name="fle" num_pb="10">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- start n1_lut6 -->
+            <mode name="n1_lut6">
+               <pb_type name="ble6" num_pb="1">
+                  <input name="in" num_pins="6"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+                     <input name="in" num_pins="6" port_class="lut_in"/>
+                     <output name="out" num_pins="1" port_class="lut_out"/>
+                     <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                     </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                     <input name="D" num_pins="1" port_class="D"/>
+                     <output name="Q" num_pins="1" port_class="Q"/>
+                     <clock name="clk" num_pins="1" port_class="clock"/>
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                     <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+                     <direct name="direct2" input="lut6.out" output="ff.D">
+                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+                     </direct>
+                     <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+                     <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+                     </mux>
+                  </interconnect>
+               </pb_type>
+               <interconnect>
+                  <direct name="direct1" input="fle.in" output="ble6.in"/>
+                  <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+                  <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+               </interconnect>
+            </mode>
+            <!-- end n1_lut6 -->
+            <!-- start n2_lut5 -->
+            <mode name="n2_lut5">
+               <pb_type name="ble5" num_pb="2">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                     <input name="in" num_pins="5" port_class="lut_in"/>
+                     <output name="out" num_pins="1" port_class="lut_out"/>
+                     <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                     </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                     <input name="D" num_pins="1" port_class="D"/>
+                     <output name="Q" num_pins="1" port_class="Q"/>
+                     <clock name="clk" num_pins="1" port_class="clock"/>
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                     <direct name="direct1" input="ble5.in" output="lut5[0:0].in"/>
+                     <direct name="direct2" input="lut5.out" output="ff.D">
+                        <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                     </direct>
+                     <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+                     <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                        <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+                     </mux>
+                  </interconnect>
+               </pb_type>
+               <interconnect>
+                  <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+                  <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+                  <direct name="direct3" input="ble5[0:0].out" output="fle.out[0:0]"/>
+                  <direct name="direct4" input="ble5[1:1].out" output="fle.out[1:1]"/>
+                  <direct name="direct5" input="fle.clk" output="ble5[0:0].clk"/>
+                  <direct name="direct6" input="fle.clk" output="ble5[1:1].clk"/>
+               </interconnect>
+            </mode>
+            <!-- end n2_lut5 -->
+         </pb_type>
+         <interconnect>
+            <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+               <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+               <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+            </complete>
+            <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+            </complete>
+            <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+            <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+         </interconnect>
+      </pb_type>
+   </complexblocklist>
+</architecture>

openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga

@@ -0,0 +1,7 @@
+# Execute VPR for architecture exploration
+
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
+    --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \
+    --constant_net_method route
+
+exit

openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml

@@ -1,287 +0,0 @@
-<?xml version="1.0" ?><!-- 
-  Architecture with no fracturable LUTs
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
---><architecture> 
-     <models>  
-          <!-- A virtual model for I/O to be used in the physical mode of io block -->  
-          <model name="io">   
-               <input_ports>    
-                    <port name="outpad"/>    
-               </input_ports>   
-               <output_ports>    
-                    <port name="inpad"/>    
-               </output_ports>   
-          </model>  
-     </models> 
-     <tiles>  
-          <tile name="io" area="0">   <sub_tile name="io" capacity="8">    
-                <equivalent_sites>     
-                     <site pb_type="io"/>     
-                </equivalent_sites>    
-                <input name="outpad" num_pins="1"/>    
-                <output name="inpad" num_pins="1"/>    
-                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>    
-                <pinlocations pattern="custom">     
-                     <loc side="left">io.outpad io.inpad</loc>     
-                     <loc side="top">io.outpad io.inpad</loc>     
-                     <loc side="right">io.outpad io.inpad</loc>     
-                     <loc side="bottom">io.outpad io.inpad</loc>     
-                </pinlocations>    
-           </sub_tile>  </tile>  
-          <tile name="clb" area="53894">   <sub_tile name="clb">    
-                <equivalent_sites>     
-                     <site pb_type="clb"/>     
-                </equivalent_sites>    
-                <input name="I" num_pins="40" equivalent="full"/>    
-                <output name="O" num_pins="10" equivalent="none"/>    
-                <clock name="clk" num_pins="1"/>    
-                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>    
-                <pinlocations pattern="spread"/>    
-           </sub_tile>  </tile>  
-     </tiles> 
-     <!-- ODIN II specific config ends --> 
-     <!-- Physical descriptions begin --> 
-     <layout tileable="true">  
-          <auto_layout aspect_ratio="1.0">   
-               <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->   
-               <perimeter type="io" priority="100"/>   
-               <corners type="EMPTY" priority="101"/>   
-               <!--Fill with 'clb'-->   
-               <fill type="clb" priority="10"/>   
-          </auto_layout>  
-     </layout> 
-     <device>  
-          <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->  
-          <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>  
-          <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	  -->  
-          <area grid_logic_tile_area="0"/>  
-          <chan_width_distr>   
-               <x distr="uniform" peak="1.000000"/>   
-               <y distr="uniform" peak="1.000000"/>   
-          </chan_width_distr>  
-          <switch_block type="wilton" fs="3"/>  
-          <connection_block input_switch_name="ipin_cblock"/>  
-     </device> 
-     <switchlist>  
-          <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->  
-          <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>  
-          <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->  
-          <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>  
-     </switchlist> 
-     <segmentlist>  
-          <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->  
-          <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">   
-               <mux name="0"/>   
-               <sb type="pattern">1 1 1 1 1</sb>   
-               <cb type="pattern">1 1 1 1</cb>   
-          </segment>  
-     </segmentlist> 
-     <complexblocklist>  
-          <!-- Define I/O pads begin -->  
-          <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->  
-          <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->  
-          <pb_type name="io">   
-               <input name="outpad" num_pins="1"/>   
-               <output name="inpad" num_pins="1"/>   
-               <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->   
-               <mode name="physical" disable_packing="true">    
-                    <pb_type name="iopad" blif_model=".subckt io" num_pb="1">     
-                         <input name="outpad" num_pins="1"/>     
-                         <output name="inpad" num_pins="1"/>     
-                    </pb_type>    
-                    <interconnect>     
-                         <direct name="outpad" input="io.outpad" output="iopad.outpad">      
-                              <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>      
-                         </direct>     
-                         <direct name="inpad" input="iopad.inpad" output="io.inpad">      
-                              <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>      
-                         </direct>     
-                    </interconnect>    
-               </mode>   
-               <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->   
-               <mode name="inpad">    
-                    <pb_type name="inpad" blif_model=".input" num_pb="1">     
-                         <output name="inpad" num_pins="1"/>     
-                    </pb_type>    
-                    <interconnect>     
-                         <direct name="inpad" input="inpad.inpad" output="io.inpad">      
-                              <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>      
-                         </direct>     
-                    </interconnect>    
-               </mode>   
-               <mode name="outpad">    
-                    <pb_type name="outpad" blif_model=".output" num_pb="1">     
-                         <input name="outpad" num_pins="1"/>     
-                    </pb_type>    
-                    <interconnect>     
-                         <direct name="outpad" input="io.outpad" output="outpad.outpad">      
-                              <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>      
-                         </direct>     
-                    </interconnect>    
-               </mode>   
-               <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->   
-               <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->   
-               <!-- Place I/Os on the sides of the FPGA -->   
-               <power method="ignore"/>   
-          </pb_type>  
-          <!-- Define I/O pads ends -->  
-          <!-- Define general purpose logic block (CLB) begin -->  
-          <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->  
-          <pb_type name="clb">   
-               <input name="I" num_pins="40" equivalent="full"/>   
-               <output name="O" num_pins="10" equivalent="none"/>   
-               <clock name="clk" num_pins="1"/>   
-               <!-- Describe basic logic element.  
-             Each basic logic element has a 6-LUT that can be optionally registered
-        -->   
-               <pb_type name="fle" num_pb="10">    
-                    <input name="in" num_pins="6"/>    
-                    <output name="out" num_pins="1"/>    
-                    <clock name="clk" num_pins="1"/>    
-                    <!-- 6-LUT mode definition begin -->    
-                    <mode name="n1_lut6">     
-                         <!-- Define 6-LUT mode -->     
-                         <pb_type name="ble6" num_pb="1">      
-                              <input name="in" num_pins="6"/>      
-                              <output name="out" num_pins="1"/>      
-                              <clock name="clk" num_pins="1"/>      
-                              <!-- Define LUT -->      
-                              <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">       
-                                   <input name="in" num_pins="6" port_class="lut_in"/>       
-                                   <output name="out" num_pins="1" port_class="lut_out"/>       
-                                   <!-- LUT timing using delay matrix -->       
-                                   <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->       
-                                   <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                            </delay_matrix>       
-                              </pb_type>      
-                              <!-- Define flip-flop -->      
-                              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">       
-                                   <input name="D" num_pins="1" port_class="D"/>       
-                                   <output name="Q" num_pins="1" port_class="Q"/>       
-                                   <clock name="clk" num_pins="1" port_class="clock"/>       
-                                   <T_setup value="66e-12" port="ff.D" clock="clk"/>       
-                                   <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>       
-                              </pb_type>      
-                              <interconnect>       
-                                   <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>       
-                                   <direct name="direct2" input="lut6.out" output="ff.D">        
-                                        <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->        
-                                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>        
-                                   </direct>       
-                                   <direct name="direct3" input="ble6.clk" output="ff.clk"/>       
-                                   <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">        
-                                        <!-- LUT to output is faster than FF to output on a Stratix IV -->        
-                                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>        
-                                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>        
-                                   </mux>       
-                              </interconnect>      
-                         </pb_type>     
-                         <interconnect>      
-                              <direct name="direct1" input="fle.in" output="ble6.in"/>      
-                              <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>      
-                              <direct name="direct3" input="fle.clk" output="ble6.clk"/>      
-                         </interconnect>     
-                    </mode>    
-                    <!-- 6-LUT mode definition end -->    
-               </pb_type>   
-               <interconnect>    
-                    <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
-		     The delays below come from Stratix IV. the delay through a connection block
-		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-		     delay within the crossbar is 95 ps. 
-		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-		     to get the part that should be marked on the crossbar.	 -->    
-                    <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">     
-                         <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>     
-                         <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>     
-                    </complete>    
-                    <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-                </complete>    
-                    <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-               naive specification).
-          -->    
-                    <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>    
-               </interconnect>   
-               <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->   
-               <!-- Place this general purpose logic block in any unspecified column -->   
-          </pb_type>  
-          <!-- Define general purpose logic block (CLB) ends -->  
-     </complexblocklist> 
-</architecture>

openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml

@@ -1,199 +0,0 @@
-<?xml version="1.0" ?><!-- 
-  Architecture with no fracturable LUTs
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
---><architecture> 
-     <models>  
-          <!-- A virtual model for I/O to be used in the physical mode of io block -->  
-          <model name="io">   
-               <input_ports>    
-                    <port name="outpad"/>    
-               </input_ports>   
-               <output_ports>    
-                    <port name="inpad"/>    
-               </output_ports>   
-          </model>  
-     </models> 
-     <tiles>  
-          <tile name="io" area="0">   <sub_tile name="io" capacity="8">    
-                <equivalent_sites>     
-                     <site pb_type="io"/>     
-                </equivalent_sites>    
-                <input name="outpad" num_pins="1"/>    
-                <output name="inpad" num_pins="1"/>    
-                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>    
-                <pinlocations pattern="custom">     
-                     <loc side="left">io.outpad io.inpad</loc>     
-                     <loc side="top">io.outpad io.inpad</loc>     
-                     <loc side="right">io.outpad io.inpad</loc>     
-                     <loc side="bottom">io.outpad io.inpad</loc>     
-                </pinlocations>    
-           </sub_tile>  </tile>  
-          <tile name="clb" area="53894">   <sub_tile name="clb">    
-                <equivalent_sites>     
-                     <site pb_type="clb"/>     
-                </equivalent_sites>    
-                <input name="I" num_pins="40" equivalent="full"/>    
-                <output name="O" num_pins="10" equivalent="none"/>    
-                <clock name="clk" num_pins="1"/>    
-                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>    
-                <pinlocations pattern="spread"/>    
-           </sub_tile>  </tile>  
-     </tiles> 
-     <!-- ODIN II specific config ends --> 
-     <!-- Physical descriptions begin --> 
-     <layout tileable="true">  
-          <auto_layout aspect_ratio="1.0">   
-               <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->   
-               <perimeter type="io" priority="100"/>   
-               <corners type="EMPTY" priority="101"/>   
-               <!--Fill with 'clb'-->   
-               <fill type="clb" priority="10"/>   
-          </auto_layout>  
-     </layout> 
-     <device>  
-          <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>  
-          <area grid_logic_tile_area="0"/>  
-          <chan_width_distr>   
-               <x distr="uniform" peak="1.000000"/>   
-               <y distr="uniform" peak="1.000000"/>   
-          </chan_width_distr>  
-          <switch_block type="wilton" fs="3"/>  
-          <connection_block input_switch_name="ipin_cblock"/>  
-     </device> 
-     <switchlist>  
-          <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>  
-          <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>  
-     </switchlist> 
-     <segmentlist>  
-          <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">   
-               <mux name="0"/>   
-               <sb type="pattern">1 1 1 1 1</sb>   
-               <cb type="pattern">1 1 1 1</cb>   
-          </segment>  
-     </segmentlist> 
-     <complexblocklist>  
-          <pb_type name="io">   
-               <input name="outpad" num_pins="1"/>   
-               <output name="inpad" num_pins="1"/>   
-               <mode name="physical" disable_packing="true">    
-                    <pb_type name="iopad" blif_model=".subckt io" num_pb="1">     
-                         <input name="outpad" num_pins="1"/>     
-                         <output name="inpad" num_pins="1"/>     
-                    </pb_type>    
-                    <interconnect>     
-                         <direct name="outpad" input="io.outpad" output="iopad.outpad">      
-                              <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>      
-                         </direct>     
-                         <direct name="inpad" input="iopad.inpad" output="io.inpad">      
-                              <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>      
-                         </direct>     
-                    </interconnect>    
-               </mode>   
-               <mode name="inpad">    
-                    <pb_type name="inpad" blif_model=".input" num_pb="1">     
-                         <output name="inpad" num_pins="1"/>     
-                    </pb_type>    
-                    <interconnect>     
-                         <direct name="inpad" input="inpad.inpad" output="io.inpad">      
-                              <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>      
-                         </direct>     
-                    </interconnect>    
-               </mode>   
-               <mode name="outpad">    
-                    <pb_type name="outpad" blif_model=".output" num_pb="1">     
-                         <input name="outpad" num_pins="1"/>     
-                    </pb_type>    
-                    <interconnect>     
-                         <direct name="outpad" input="io.outpad" output="outpad.outpad">      
-                              <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>      
-                         </direct>     
-                    </interconnect>    
-               </mode>   
-               <power method="ignore"/>   
-          </pb_type>  
-          <pb_type name="clb">   
-               <input name="I" num_pins="40" equivalent="full"/>   
-               <output name="O" num_pins="10" equivalent="none"/>   
-               <clock name="clk" num_pins="1"/>   
-               <!-- Describe basic logic element.  
-             Each basic logic element has a 6-LUT that can be optionally registered
-        -->   
-               <pb_type name="fle" num_pb="10">    
-                    <input name="in" num_pins="6"/>    
-                    <output name="out" num_pins="1"/>    
-                    <clock name="clk" num_pins="1"/>    
-                    <!-- 6-LUT mode definition begin -->    
-                    <mode name="n1_lut6">     
-                         <!-- Define 6-LUT mode -->     
-                         <pb_type name="ble6" num_pb="1">      
-                              <input name="in" num_pins="6"/>      
-                              <output name="out" num_pins="1"/>      
-                              <clock name="clk" num_pins="1"/>      
-                              <!-- Define LUT -->      
-                              <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">       
-                                   <input name="in" num_pins="6" port_class="lut_in"/>       
-                                   <output name="out" num_pins="1" port_class="lut_out"/>       
-                                   <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                                261e-12
-                                261e-12
-                                261e-12
-                                261e-12
-                                261e-12
-                                261e-12
-                            </delay_matrix>       
-                              </pb_type>      
-                              <!-- Define flip-flop -->      
-                              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">       
-                                   <input name="D" num_pins="1" port_class="D"/>       
-                                   <output name="Q" num_pins="1" port_class="Q"/>       
-                                   <clock name="clk" num_pins="1" port_class="clock"/>       
-                                   <T_setup value="66e-12" port="ff.D" clock="clk"/>       
-                                   <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>       
-                              </pb_type>      
-                              <interconnect>       
-                                   <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>       
-                                   <direct name="direct2" input="lut6.out" output="ff.D">        
-                                        <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->        
-                                        <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>        
-                                   </direct>       
-                                   <direct name="direct3" input="ble6.clk" output="ff.clk"/>       
-                                   <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">        
-                                        <!-- LUT to output is faster than FF to output on a Stratix IV -->        
-                                        <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>        
-                                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>        
-                                   </mux>       
-                              </interconnect>      
-                         </pb_type>     
-                         <interconnect>      
-                              <direct name="direct1" input="fle.in" output="ble6.in"/>      
-                              <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>      
-                              <direct name="direct3" input="fle.clk" output="ble6.clk"/>      
-                         </interconnect>     
-                    </mode>    
-                    <!-- 6-LUT mode definition end -->    
-               </pb_type>   
-               <interconnect>    
-                    <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">     
-                         <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>     
-                         <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>     
-                    </complete>    
-                    <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-                </complete>    
-                    <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>    
-               </interconnect>   
-               <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->   
-               <!-- Place this general purpose logic block in any unspecified column -->   
-          </pb_type>  
-     </complexblocklist> 
-</architecture>

vtr-verilog-to-routing

@@ -1 +1 @@
-Subproject commit caf364c820c720776ce031361275e782a0d69402
+Subproject commit 9e53e9a0a7c18ba9a16ea08678da726b98c669d4

yosys

@@ -1 +1 @@
-Subproject commit f109fa3d4c56fe33bc626c298e04d45ae510dd0e
+Subproject commit b58664d441764b4de1d01c4efcdd45094ba71535

yosys-plugins

@@ -1 +1 @@
-Subproject commit b5d9b3cc59e0c897a8449ef79acdec4d415f1807
+Subproject commit 24755e3b43400ad25e90fe01cc764a28a12de999