From 211eeab217b2e57c10a76fb469258d8258fa5143 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 2 Feb 2023 07:03:07 +0000 Subject: [PATCH 01/52] Bump vtr-verilog-to-routing from `caf364c` to `62e42cf` Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `caf364c` to `62e42cf`. - [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases) - [Commits](https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/caf364c820c720776ce031361275e782a0d69402...62e42cfbf7c4c0ddeb9ec79691a729a9afae1c5c) --- updated-dependencies: - dependency-name: vtr-verilog-to-routing dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index caf364c82..62e42cfbf 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit caf364c820c720776ce031361275e782a0d69402 +Subproject commit 62e42cfbf7c4c0ddeb9ec79691a729a9afae1c5c From cfdea5d0dd0a89aa6fef6254615b898b5fb7e6da Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 2 Feb 2023 07:03:12 +0000 Subject: [PATCH 02/52] Bump yosys-plugins from `b5d9b3c` to `a20c6a9` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `b5d9b3c` to `a20c6a9`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/b5d9b3cc59e0c897a8449ef79acdec4d415f1807...a20c6a96d9fd4b8989940a6608501784e02e78b1) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index b5d9b3cc5..a20c6a96d 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit b5d9b3cc59e0c897a8449ef79acdec4d415f1807 +Subproject commit a20c6a96d9fd4b8989940a6608501784e02e78b1 From 2f66d84ecfacdf9440ec442aee9423d6e62e32c9 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 2 Feb 2023 15:43:40 -0700 Subject: [PATCH 03/52] Updated node version for binder run --- Dockerfile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index d6f52e9cc..28094b21b 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,7 +1,8 @@ FROM ghcr.io/lnis-uofu/openfpga-master:latest # Install node js -RUN curl -sL https://deb.nodesource.com/setup_12.x | bash - +USER root +RUN curl -sL https://deb.nodesource.com/setup_14.x | bash - RUN curl -fsSL https://code-server.dev/install.sh | sh RUN apt-get install -y nodejs RUN apt-get install tree From 40470ceb0cc5f3ba23c40d4dc9f6030f3e5d8048 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 2 Feb 2023 15:49:21 -0700 Subject: [PATCH 04/52] Removed duplicate user creation --- Dockerfile | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/Dockerfile b/Dockerfile index 28094b21b..f052ae613 100644 --- a/Dockerfile +++ b/Dockerfile @@ -14,18 +14,13 @@ ENV USER ${NB_USER} ENV NB_UID ${NB_UID} ENV HOME /home/${NB_USER} -RUN adduser --disabled-password \ - --gecos "Default user" \ - --uid ${NB_UID} \ - ${NB_USER} - -USER root RUN chown -R ${NB_UID} ${HOME} RUN chown -R ${NB_UID} /opt/openfpga USER ${NB_USER} ENV PATH $PATH:/home/${NB_USER}/.local/bin +RUN python3 -m pip install --upgrade pip RUN python3 -m pip install --user --no-cache-dir notebook RUN python3 -m pip install --user --no-cache-dir jupyterlab RUN python3 -m pip install --user --no-cache-dir jupyterhub From 8089fd9e3c5258eaedb76827e28982125e4a3d8c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 2 Feb 2023 16:12:53 -0700 Subject: [PATCH 05/52] Changed work directory of binder run --- Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/Dockerfile b/Dockerfile index f052ae613..3c9a13e4c 100644 --- a/Dockerfile +++ b/Dockerfile @@ -31,6 +31,7 @@ RUN npm install @jupyterlab/server-proxy RUN jupyter serverextension enable --py jupyter_server_proxy RUN jupyter labextension install @jupyterlab/server-proxy RUN jupyter lab build +WORKDIR /opt/openfpga/ RUN git reset --hard HEAD # Set up terminal From 0e541dedd45e51c6922d2a2a95ba11792fba5561 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 2 Feb 2023 20:43:40 -0700 Subject: [PATCH 06/52] Updating dockers --- Dockerfile | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 3c9a13e4c..da35bda14 100644 --- a/Dockerfile +++ b/Dockerfile @@ -8,14 +8,24 @@ RUN apt-get install -y nodejs RUN apt-get install tree RUN code-server --install-extension ms-python.python -ARG NB_USER=openfpga_user +RUN usermod -u 2000 openfpga_user +RUN groupmod -g 2000 openfpga_user + +ARG NB_USER=of_user ARG NB_UID=1000 ENV USER ${NB_USER} ENV NB_UID ${NB_UID} ENV HOME /home/${NB_USER} +RUN adduser --disabled-password \ + --gecos "Default user" \ + --uid ${NB_UID} \ + ${NB_USER} + RUN chown -R ${NB_UID} ${HOME} RUN chown -R ${NB_UID} /opt/openfpga + +WORKDIR ${HOME} USER ${NB_USER} ENV PATH $PATH:/home/${NB_USER}/.local/bin From 171a3f4a27b894cff5e05cecec9066991065651e Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 3 Feb 2023 14:19:43 -0700 Subject: [PATCH 07/52] Updated installation process --- Dockerfile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Dockerfile b/Dockerfile index da35bda14..1a155fca4 100644 --- a/Dockerfile +++ b/Dockerfile @@ -7,11 +7,12 @@ RUN curl -fsSL https://code-server.dev/install.sh | sh RUN apt-get install -y nodejs RUN apt-get install tree RUN code-server --install-extension ms-python.python +RUN code-server --install-extension mechatroner RUN usermod -u 2000 openfpga_user RUN groupmod -g 2000 openfpga_user -ARG NB_USER=of_user +ARG NB_USER=user_openfpga ARG NB_UID=1000 ENV USER ${NB_USER} ENV NB_UID ${NB_UID} @@ -34,12 +35,12 @@ RUN python3 -m pip install --upgrade pip RUN python3 -m pip install --user --no-cache-dir notebook RUN python3 -m pip install --user --no-cache-dir jupyterlab RUN python3 -m pip install --user --no-cache-dir jupyterhub +RUN python3 -m pip install --user --no-cache-dir "jupyter-server<2.0.0" RUN python3 -m pip install --user --no-cache-dir jupyter-server-proxy RUN python3 -m pip install --user --no-cache-dir jupyter-vscode-proxy RUN npm install @jupyterlab/server-proxy RUN jupyter serverextension enable --py jupyter_server_proxy -RUN jupyter labextension install @jupyterlab/server-proxy RUN jupyter lab build WORKDIR /opt/openfpga/ RUN git reset --hard HEAD From 3d665778b19ecf4c64350b717220ed644d8e41ad Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 4 Feb 2023 05:12:58 +0000 Subject: [PATCH 08/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 6186deafa..a26faa2e9 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.672 +1.2.686 From f38e8aefb372221c8ae68e2c6b8e826d1ceefe6c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Feb 2023 22:10:40 -0800 Subject: [PATCH 09/52] [script] now yosys is installed to the build directory --- CMakeLists.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 193ac953e..e23d09b1b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -312,15 +312,15 @@ endif() # we will check if yosys already exist. if not then build it if (OPENFPGA_WITH_YOSYS) - if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys) + if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys/install/bin/yosys) message(STATUS "Yosys pre-build exist so skipping it") else () # run makefile provided, we pass-on the options to the local make file add_custom_target( yosys ALL COMMAND $(MAKE) config-gcc - COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys + COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys/install + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/yosys COMMENT "Compile Yosys with given Makefile" ) # yosys compilation ends @@ -329,9 +329,9 @@ if (OPENFPGA_WITH_YOSYS) if (OPENFPGA_WITH_YOSYS_PLUGIN) add_custom_target( yosys-plugins ALL - COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins - DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys + COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_BINARY_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql" + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/yosys-plugins + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys/install/bin/yosys COMMENT "Compile Yosys-plugins with given Makefile" ) add_dependencies(yosys-plugins yosys) From ff31a7b82869d3ab014687c1e463f15541d1ea6d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Feb 2023 22:12:03 -0800 Subject: [PATCH 10/52] [script] fixed the path to yosys bin for openfpga flow --- openfpga_flow/misc/fpgaflow_default_tool_path.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 9d0c07982..042c8f159 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -1,13 +1,13 @@ # Standard Configuration Example [CAD_TOOLS_PATH] openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga -yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys +yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/install/bin/yosys misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe -abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc +abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/install/bin/yosys-abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc -abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc -vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr +abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc +vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl iverilog_path = iverilog From 305c033eb599522ab8b2edd6bf75c4c20be35303 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Feb 2023 22:13:53 -0800 Subject: [PATCH 11/52] [script] fixed a few bugs --- CMakeLists.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index e23d09b1b..7b953d9b2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -312,15 +312,15 @@ endif() # we will check if yosys already exist. if not then build it if (OPENFPGA_WITH_YOSYS) - if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys/install/bin/yosys) + if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys) message(STATUS "Yosys pre-build exist so skipping it") else () # run makefile provided, we pass-on the options to the local make file add_custom_target( yosys ALL COMMAND $(MAKE) config-gcc - COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys/install - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/yosys + COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys COMMENT "Compile Yosys with given Makefile" ) # yosys compilation ends @@ -329,9 +329,9 @@ if (OPENFPGA_WITH_YOSYS) if (OPENFPGA_WITH_YOSYS_PLUGIN) add_custom_target( yosys-plugins ALL - COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_BINARY_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/yosys-plugins - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys/install/bin/yosys + COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_BINARY_DIR}/yosys EXTRA_FLAGS="-DPASS_NAME=synth_ql" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys COMMENT "Compile Yosys-plugins with given Makefile" ) add_dependencies(yosys-plugins yosys) From 9c8ece4e147a48fe52f0d71d382cc39abf17c38e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Feb 2023 22:49:08 -0800 Subject: [PATCH 12/52] [script] fixing some bugs --- CMakeLists.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7b953d9b2..35a2296c7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -312,14 +312,14 @@ endif() # we will check if yosys already exist. if not then build it if (OPENFPGA_WITH_YOSYS) - if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys) + if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys/bin/yosys) message(STATUS "Yosys pre-build exist so skipping it") else () # run makefile provided, we pass-on the options to the local make file add_custom_target( yosys ALL COMMAND $(MAKE) config-gcc - COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys + COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys/ WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys COMMENT "Compile Yosys with given Makefile" ) @@ -331,7 +331,7 @@ if (OPENFPGA_WITH_YOSYS) yosys-plugins ALL COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_BINARY_DIR}/yosys EXTRA_FLAGS="-DPASS_NAME=synth_ql" WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys/bin/yosys COMMENT "Compile Yosys-plugins with given Makefile" ) add_dependencies(yosys-plugins yosys) From 57cec96d7eaa40ccbc18c3e0c7b456cd2fd77ab7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Feb 2023 22:54:22 -0800 Subject: [PATCH 13/52] [script] wrong path to yosys bin --- openfpga_flow/misc/fpgaflow_default_tool_path.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 042c8f159..5958d1b6b 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -1,10 +1,10 @@ # Standard Configuration Example [CAD_TOOLS_PATH] openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga -yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/install/bin/yosys +yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe -abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/install/bin/yosys-abc +abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys-abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr From b41a77e7123f287db9f52ce4ff44a737fa0814ce Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 4 Feb 2023 13:18:42 -0800 Subject: [PATCH 14/52] [script] correct paths related to yosys in docker image and ci --- .github/workflows/build.yml | 14 +++++++------- docker/Dockerfile.master | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 9e293a2a9..e5223f0fe 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -151,8 +151,8 @@ jobs: build/openfpga/libopenfpga.a build/openfpga/openfpga_shell.so build/openfpga/openfpga - yosys/install/share - yosys/install/bin + build/yosys/share + build/yosys/bin openfpga_flow openfpga.sh @@ -446,11 +446,11 @@ jobs: chmod +x build/vtr-verilog-to-routing/ace2/ace chmod +x build/vtr-verilog-to-routing/vpr/vpr chmod +x build/openfpga/openfpga - chmod +x yosys/install/bin/yosys - chmod +x yosys/install/bin/yosys-abc - chmod +x yosys/install/bin/yosys-config - chmod +x yosys/install/bin/yosys-filterlib - chmod +x yosys/install/bin/yosys-smtbmc + chmod +x build/yosys/bin/yosys + chmod +x build/yosys/bin/yosys-abc + chmod +x build/yosys/bin/yosys-config + chmod +x build/yosys/bin/yosys-filterlib + chmod +x build/yosys/bin/yosys-smtbmc - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04) shell: bash run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs diff --git a/docker/Dockerfile.master b/docker/Dockerfile.master index 50bf7e30f..769f28e1e 100644 --- a/docker/Dockerfile.master +++ b/docker/Dockerfile.master @@ -3,8 +3,8 @@ RUN mkdir -p /opt/openfpga WORKDIR /opt/openfpga COPY . /opt/openfpga RUN chmod +x build/vtr-verilog-to-routing/abc/abc build/vtr-verilog-to-routing/ace2/ace build/openfpga/openfpga build/vtr-verilog-to-routing/vpr/vpr -RUN chmod +x yosys/install/bin/yosys yosys/install/bin/yosys-abc yosys/install/bin/yosys-config yosys/install/bin/yosys-filterlib yosys/install/bin/yosys-smtbmc -ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/yosys/install/bin:${PATH}" +RUN chmod +x build/yosys/bin/yosys build/yosys/bin/yosys-abc build/yosys/bin/yosys-config build/yosys/bin/yosys-filterlib build/yosys/bin/yosys-smtbmc +ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/build/yosys/bin:${PATH}" ENV PATH="/opt/openfpga/build/vtr-verilog-to-routing/ace2:/opt/openfpga/build/vtr-verilog-to-routing/abc:/opt/openfpga/build/vtr-verilog-to-routing/vpr:${PATH}" ENV OPENFPGA_PATH="/opt/openfpga" From 509f238779294b1351fc6b0fc7752e7585fc633a Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 6 Feb 2023 00:02:18 +0000 Subject: [PATCH 15/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index a26faa2e9..6b26239fc 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.686 +1.2.695 From e9fdef0636ed20cbc0d1e040266e99d0a76429c4 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 9 Feb 2023 07:03:42 +0000 Subject: [PATCH 16/52] Bump yosys-plugins from `a20c6a9` to `08430ec` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `a20c6a9` to `08430ec`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/a20c6a96d9fd4b8989940a6608501784e02e78b1...08430ec4f53d1cf9d6a2091211d6c5ce501d5486) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index a20c6a96d..08430ec4f 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit a20c6a96d9fd4b8989940a6608501784e02e78b1 +Subproject commit 08430ec4f53d1cf9d6a2091211d6c5ce501d5486 From f14f3fdcbe2e286b9e0ef4dfb2749d4a1ffe2938 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 9 Feb 2023 07:03:46 +0000 Subject: [PATCH 17/52] Bump yosys from `f109fa3` to `b1a0111` Bumps [yosys](https://github.com/YosysHQ/yosys) from `f109fa3` to `b1a0111`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/f109fa3d4c56fe33bc626c298e04d45ae510dd0e...b1a011138ccc7ac840806d2a787f48f6baf6f107) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index f109fa3d4..b1a011138 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit f109fa3d4c56fe33bc626c298e04d45ae510dd0e +Subproject commit b1a011138ccc7ac840806d2a787f48f6baf6f107 From eb6d12861f75942a87138c90d9342eeb278caa07 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 10 Feb 2023 00:02:21 +0000 Subject: [PATCH 18/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 6b26239fc..dab54c251 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.695 +1.2.702 From 55be8f491e19f0c9dbbedcee070f723a3373f6a0 Mon Sep 17 00:00:00 2001 From: scott-temple <120586182+scott-temple@users.noreply.github.com> Date: Fri, 10 Feb 2023 10:22:37 -0700 Subject: [PATCH 19/52] fix mux syntax in circuit_model_examples the documentation is inconsistent about using underscores or dashes when describing a mux. It used one-level, but multi_level. Only underscores are valid in openfpga --- docs/source/manual/arch_lang/circuit_model_examples.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index 437cea837..94f1d5e02 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -523,9 +523,9 @@ Template .. option:: - - ``structure="tree|multi-level|one-level"`` Specify the multiplexer structure for a multiplexer. The structure option is only valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the one-level structure + - ``structure="tree|multi_level|one_level"`` Specify the multiplexer structure for a multiplexer. The structure option is only valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the one_level structure - - ``num_level=""`` Specify the number of levels when ``multi-level`` structure is selected. + - ``num_level=""`` Specify the number of levels when ``multi_level`` structure is selected. - ``add_const_input="true|false"`` Specify if an extra input should be added to the multiplexer circuits. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. @@ -563,7 +563,7 @@ The code describing this Multiplexer is: .. code-block:: xml - + From dcdf3ea3d1343905e587c64af02c143b7fa47fbd Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 11 Feb 2023 00:02:14 +0000 Subject: [PATCH 20/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index dab54c251..c66d1fd16 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.702 +1.2.706 From 2afb91596fe0d507483b8d7e0dfb60dbc4a075d7 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 18:04:54 -0700 Subject: [PATCH 21/52] Refactored run_openfpga_task.py --- openfpga_flow/scripts/run_fpga_task.py | 120 ++++++++++++++++++------- 1 file changed, 89 insertions(+), 31 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 093d32db3..bb223effa 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -67,10 +67,14 @@ parser.add_argument( ) parser.add_argument("--config", help="Override default configuration") parser.add_argument( - "--test_run", action="store_true", help="Dummy run shows final generated VPR commands" + "--test_run", + action="store_true", + help="Dummy run shows final generated VPR commands", ) parser.add_argument("--debug", action="store_true", help="Run script in debug mode") -parser.add_argument("--continue_on_fail", action="store_true", help="Exit script with return code") +parser.add_argument( + "--continue_on_fail", action="store_true", help="Exit script with return code" +) parser.add_argument( "--show_thread_logs", action="store_true", help="Skips logs from running thread" ) @@ -83,13 +87,24 @@ task_script_dir = os.path.dirname(os.path.abspath(__file__)) script_env_vars = { "PATH": { "OPENFPGA_FLOW_PATH": task_script_dir, - "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"), - "OPENFPGA_SHELLSCRIPT_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "OpenFPGAShellScripts"), - "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"), - "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"), + "VPR_ARCH_PATH": os.path.join( + "${PATH:OPENFPGA_PATH}", "openfpga_flow", "vpr_arch" + ), + "OF_ARCH_PATH": os.path.join( + "${PATH:OPENFPGA_PATH}", "openfpga_flow", "openfpga_arch" + ), + "OPENFPGA_SHELLSCRIPT_PATH": os.path.join( + "${PATH:OPENFPGA_PATH}", "openfpga_flow", "OpenFPGAShellScripts" + ), + "BENCH_PATH": os.path.join( + "${PATH:OPENFPGA_PATH}", "openfpga_flow", "benchmarks" + ), + "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "tech"), "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"), "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"), - "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir)), + "OPENFPGA_PATH": os.path.abspath( + os.path.join(task_script_dir, os.pardir, os.pardir) + ), } } config = ConfigParser(interpolation=ExtendedInterpolation()) @@ -237,7 +252,8 @@ def generate_each_task_actions(taskname): missing_section = list(set(required_sec) - set(task_conf.sections())) if missing_section: clean_up_and_exit( - "Missing sections %s" % " ".join(missing_section) + " in task configuration file" + "Missing sections %s" % " ".join(missing_section) + + " in task configuration file" ) # Declare varibles to access sections @@ -258,7 +274,9 @@ def generate_each_task_actions(taskname): clean_up_and_exit("Found duplicate architectures in config file") # Get Flow information - logger.info('Running "%s" flow', GeneralSection.get("fpga_flow", fallback="yosys_vpr")) + logger.info( + 'Running "%s" flow', GeneralSection.get("fpga_flow", fallback="yosys_vpr") + ) # Check if specified benchmark files exist benchmark_list = [] @@ -272,7 +290,8 @@ def generate_each_task_actions(taskname): files = glob.glob(eachpath) if not len(files): clean_up_and_exit( - ("No files added benchmark %s" % bech_name) + " with path %s " % (eachpath) + ("No files added benchmark %s" % bech_name) + + " with path %s " % (eachpath) ) bench_files += files @@ -308,11 +327,15 @@ def generate_each_task_actions(taskname): yosys_params_common = {} for param in yosys_params: - yosys_params_common[param.upper()] = SynthSection.get("bench_" + param + "_common") + yosys_params_common[param.upper()] = SynthSection.get( + "bench_" + param + "_common" + ) # Individual benchmark configuration CurrBenchPara["files"] = bench_files - CurrBenchPara["top_module"] = SynthSection.get(bech_name + "_top", fallback="top") + CurrBenchPara["top_module"] = SynthSection.get( + bech_name + "_top", fallback="top" + ) CurrBenchPara["ys_script"] = SynthSection.get( bech_name + "_yosys", fallback=ys_for_task_common ) @@ -337,7 +360,8 @@ def generate_each_task_actions(taskname): if GeneralSection.getboolean("power_analysis"): if not SynthSection.get(bech_name + "_act"): clean_up_and_exit( - "Missing argument %s" % (bech_name + "_act") + "for vpr_blif flow" + "Missing argument %s" % (bech_name + "_act") + + "for vpr_blif flow" ) CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act") else: @@ -345,7 +369,9 @@ def generate_each_task_actions(taskname): if not SynthSection.get(bech_name + "_act"): CurrBenchPara["activity_file"] = bech_name + "_act" else: - CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act") + CurrBenchPara["activity_file"] = SynthSection.get( + bech_name + "_act" + ) # Check if base verilog file exists if not SynthSection.get(bech_name + "_verilog"): @@ -381,13 +407,16 @@ def generate_each_task_actions(taskname): # architecture, benchmark and parameters # Create run_job object [arch, bench, run_dir, commnad] flow_run_cmd_list = [] - for indx, arch in enumerate(archfile_list): - for bench in benchmark_list: + for bench in benchmark_list: + for indx, arch in enumerate(archfile_list): for lbl, param in bench["script_params"].items(): if benchmark_top_module_count.count(bench["top_module"]) > 1: flow_run_dir = get_flow_rundir( arch, - "bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"], + "bench" + + str(benchmark_list.index(bench)) + + "_" + + bench["top_module"], lbl, ) else: @@ -400,6 +429,7 @@ def generate_each_task_actions(taskname): param=param, task_conf=task_conf, ) + command += ["--flow_config", curr_task_conf_file] flow_run_cmd_list.append( { "arch": arch, @@ -506,13 +536,21 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): if args.debug: command += ["--debug"] + return command def strip_child_logger_info(line): try: logtype, message = line.split(" - ", 1) - lognumb = {"CRITICAL": 50, "ERROR": 40, "WARNING": 30, "INFO": 20, "DEBUG": 10, "NOTSET": 0} + lognumb = { + "CRITICAL": 50, + "ERROR": 40, + "WARNING": 30, + "INFO": 20, + "DEBUG": 10, + "NOTSET": 0, + } logger.log(lognumb[logtype.strip().upper()], message) except: logger.info(line) @@ -555,7 +593,11 @@ def run_single_script(s, eachJob, job_list): os._exit(1) eachJob["endtime"] = time.time() timediff = timedelta(seconds=(eachJob["endtime"] - eachJob["starttime"])) - timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules else str(timediff) + timestr = ( + humanize.naturaldelta(timediff) + if "humanize" in sys.modules + else str(timediff) + ) logger.info( "%s Finished with returncode %d, Time Taken %s ", thread_name, @@ -572,7 +614,9 @@ def run_actions(job_list): thread_list = [] for _, eachjob in enumerate(job_list): t = threading.Thread( - target=run_single_script, name=eachjob["name"], args=(thread_sema, eachjob, job_list) + target=run_single_script, + name=eachjob["name"], + args=(thread_sema, eachjob, job_list), ) t.start() thread_list.append(t) @@ -581,6 +625,9 @@ def run_actions(job_list): def collect_results(job_run_list): + """ + Collect performance numbers from vpr_stat.result file + """ task_result = [] for run in job_run_list: if not run["status"]: @@ -588,25 +635,36 @@ def collect_results(job_run_list): continue # Check if any result file exist if not glob.glob(os.path.join(run["run_dir"], "*.result")): - logger.info("No result files found for %s" % run["name"]) + logger.info("No result files found for %s", run["name"]) + continue # Read and merge result file - vpr_res = ConfigParser(allow_no_value=True, interpolation=ExtendedInterpolation()) - vpr_res.read_file(open(os.path.join(run["run_dir"], "vpr_stat.result"))) + vpr_res = ConfigParser( + allow_no_value=True, interpolation=ExtendedInterpolation() + ) + vpr_result_file = os.path.join(run["run_dir"], "vpr_stat.result") + vpr_res.read_file(open(vpr_result_file, encoding="UTF-8")) result = OrderedDict() result["name"] = run["name"] result["TotalRunTime"] = int(run["endtime"] - run["starttime"]) result.update(vpr_res["RESULTS"]) task_result.append(result) - colnames = [] - for eachLbl in task_result: - colnames.extend(eachLbl.keys()) - if len(task_result): - with open("task_result.csv", "w", newline="") as csvfile: - writer = csv.DictWriter(csvfile, extrasaction="ignore", fieldnames=list(colnames)) + + colnames = [] + # Extract all column names + for each_metric in task_result: + colnames.extend(set(each_metric.keys()) - {"name", "TotalRunTime"}) + colnames = sorted(list(set(colnames))) + if len(task_result) > 0: + with open("task_result.csv", "w", encoding="UTF-8", newline="") as csvfile: + writer = csv.DictWriter( + csvfile, + extrasaction="ignore", + fieldnames=["name", "TotalRunTime"] + colnames, + ) writer.writeheader() - for eachResult in task_result: - writer.writerow(eachResult) + for each in task_result: + writer.writerow(each) if __name__ == "__main__": From a6263c44af549749d75124d9b844fd116dd44487 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 18:12:04 -0700 Subject: [PATCH 22/52] Updated format --- openfpga_flow/scripts/run_fpga_flow.py | 4 +- openfpga_flow/scripts/run_fpga_task.py | 60 +++++++------------------- 2 files changed, 17 insertions(+), 47 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3a936b9e7..23a655e02 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -395,7 +395,7 @@ def main(): def check_required_file(): - """ Function ensure existace of all required files for the script """ + """Function ensure existace of all required files for the script""" files_dict = { "CAD TOOL PATH": os.path.join( flow_script_dir, os.pardir, "misc", "fpgaflow_default_tool_path.conf" @@ -407,7 +407,7 @@ def check_required_file(): def read_script_config(): - """ This fucntion reads default CAD tools path from configuration file """ + """This fucntion reads default CAD tools path from configuration file""" global config, cad_tools config = ConfigParser(interpolation=ExtendedInterpolation()) config.read_dict(script_env_vars) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index bb223effa..e215a3f50 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -72,9 +72,7 @@ parser.add_argument( help="Dummy run shows final generated VPR commands", ) parser.add_argument("--debug", action="store_true", help="Run script in debug mode") -parser.add_argument( - "--continue_on_fail", action="store_true", help="Exit script with return code" -) +parser.add_argument("--continue_on_fail", action="store_true", help="Exit script with return code") parser.add_argument( "--show_thread_logs", action="store_true", help="Skips logs from running thread" ) @@ -87,24 +85,16 @@ task_script_dir = os.path.dirname(os.path.abspath(__file__)) script_env_vars = { "PATH": { "OPENFPGA_FLOW_PATH": task_script_dir, - "VPR_ARCH_PATH": os.path.join( - "${PATH:OPENFPGA_PATH}", "openfpga_flow", "vpr_arch" - ), - "OF_ARCH_PATH": os.path.join( - "${PATH:OPENFPGA_PATH}", "openfpga_flow", "openfpga_arch" - ), + "VPR_ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "vpr_arch"), + "OF_ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "openfpga_arch"), "OPENFPGA_SHELLSCRIPT_PATH": os.path.join( "${PATH:OPENFPGA_PATH}", "openfpga_flow", "OpenFPGAShellScripts" ), - "BENCH_PATH": os.path.join( - "${PATH:OPENFPGA_PATH}", "openfpga_flow", "benchmarks" - ), + "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "benchmarks"), "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "tech"), "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"), "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"), - "OPENFPGA_PATH": os.path.abspath( - os.path.join(task_script_dir, os.pardir, os.pardir) - ), + "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir)), } } config = ConfigParser(interpolation=ExtendedInterpolation()) @@ -252,8 +242,7 @@ def generate_each_task_actions(taskname): missing_section = list(set(required_sec) - set(task_conf.sections())) if missing_section: clean_up_and_exit( - "Missing sections %s" % " ".join(missing_section) - + " in task configuration file" + "Missing sections %s" % " ".join(missing_section) + " in task configuration file" ) # Declare varibles to access sections @@ -274,9 +263,7 @@ def generate_each_task_actions(taskname): clean_up_and_exit("Found duplicate architectures in config file") # Get Flow information - logger.info( - 'Running "%s" flow', GeneralSection.get("fpga_flow", fallback="yosys_vpr") - ) + logger.info('Running "%s" flow', GeneralSection.get("fpga_flow", fallback="yosys_vpr")) # Check if specified benchmark files exist benchmark_list = [] @@ -290,8 +277,7 @@ def generate_each_task_actions(taskname): files = glob.glob(eachpath) if not len(files): clean_up_and_exit( - ("No files added benchmark %s" % bech_name) - + " with path %s " % (eachpath) + ("No files added benchmark %s" % bech_name) + " with path %s " % (eachpath) ) bench_files += files @@ -327,15 +313,11 @@ def generate_each_task_actions(taskname): yosys_params_common = {} for param in yosys_params: - yosys_params_common[param.upper()] = SynthSection.get( - "bench_" + param + "_common" - ) + yosys_params_common[param.upper()] = SynthSection.get("bench_" + param + "_common") # Individual benchmark configuration CurrBenchPara["files"] = bench_files - CurrBenchPara["top_module"] = SynthSection.get( - bech_name + "_top", fallback="top" - ) + CurrBenchPara["top_module"] = SynthSection.get(bech_name + "_top", fallback="top") CurrBenchPara["ys_script"] = SynthSection.get( bech_name + "_yosys", fallback=ys_for_task_common ) @@ -360,8 +342,7 @@ def generate_each_task_actions(taskname): if GeneralSection.getboolean("power_analysis"): if not SynthSection.get(bech_name + "_act"): clean_up_and_exit( - "Missing argument %s" % (bech_name + "_act") - + "for vpr_blif flow" + "Missing argument %s" % (bech_name + "_act") + "for vpr_blif flow" ) CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act") else: @@ -369,9 +350,7 @@ def generate_each_task_actions(taskname): if not SynthSection.get(bech_name + "_act"): CurrBenchPara["activity_file"] = bech_name + "_act" else: - CurrBenchPara["activity_file"] = SynthSection.get( - bech_name + "_act" - ) + CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act") # Check if base verilog file exists if not SynthSection.get(bech_name + "_verilog"): @@ -413,10 +392,7 @@ def generate_each_task_actions(taskname): if benchmark_top_module_count.count(bench["top_module"]) > 1: flow_run_dir = get_flow_rundir( arch, - "bench" - + str(benchmark_list.index(bench)) - + "_" - + bench["top_module"], + "bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"], lbl, ) else: @@ -593,11 +569,7 @@ def run_single_script(s, eachJob, job_list): os._exit(1) eachJob["endtime"] = time.time() timediff = timedelta(seconds=(eachJob["endtime"] - eachJob["starttime"])) - timestr = ( - humanize.naturaldelta(timediff) - if "humanize" in sys.modules - else str(timediff) - ) + timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules else str(timediff) logger.info( "%s Finished with returncode %d, Time Taken %s ", thread_name, @@ -639,9 +611,7 @@ def collect_results(job_run_list): continue # Read and merge result file - vpr_res = ConfigParser( - allow_no_value=True, interpolation=ExtendedInterpolation() - ) + vpr_res = ConfigParser(allow_no_value=True, interpolation=ExtendedInterpolation()) vpr_result_file = os.path.join(run["run_dir"], "vpr_stat.result") vpr_res.read_file(open(vpr_result_file, encoding="UTF-8")) result = OrderedDict() From 6a48f1eb0546ec3ae74b3fdf02bb58487eb11423 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 18:24:20 -0700 Subject: [PATCH 23/52] Updated demo projects --- Dockerfile | 4 +- docs/source/conf.py | 21 +- .../getting_started/shell_shortcuts.rst | 23 +- openfpga.sh | 19 +- .../config/task.conf | 49 ++ .../k6_N10_tileable.xml | 198 ++++++++ .../k6_frac_N10_tileable.xml | 245 +++++++++ .../openfpga_arch.xml | 200 ++++++++ .../vtr_benchmark_template_script.openfpga | 7 + .../vpr_blif_template/arch/vpr_arch.xml | 472 +++++++----------- .../vpr_blif_template/config/task.conf | 18 +- .../vpr_blif_template/example_script.openfpga | 7 +- .../micro_benchmark/mult8/mult8.v | 22 + .../yosys_vpr_template/arch/openfpga_arch.xml | 29 +- .../yosys_vpr_template/arch/vpr_arch.xml | 423 ++++++++-------- 15 files changed, 1209 insertions(+), 528 deletions(-) create mode 100644 openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf create mode 100644 openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml create mode 100644 openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml create mode 100644 openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/openfpga_arch.xml create mode 100644 openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v diff --git a/Dockerfile b/Dockerfile index 1a155fca4..22d150d40 100644 --- a/Dockerfile +++ b/Dockerfile @@ -7,7 +7,9 @@ RUN curl -fsSL https://code-server.dev/install.sh | sh RUN apt-get install -y nodejs RUN apt-get install tree RUN code-server --install-extension ms-python.python -RUN code-server --install-extension mechatroner +RUN code-server --install-extension mechatroner.rainbow-csv +RUN code-server --install-extension wavetrace.wavetrace +RUN code-server --install-extension dotjoshjohnson.xml RUN usermod -u 2000 openfpga_user RUN groupmod -g 2000 openfpga_user diff --git a/docs/source/conf.py b/docs/source/conf.py index 02a4256b8..821dcb4b2 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -185,7 +185,7 @@ texinfo_documents = [ ] -bibtex_bibfiles = ["z_reference.bib"] +bibtex_bibfiles = ["./appendix/z_reference.bib"] # -- Options for Epub output ------------------------------------------------- @@ -203,3 +203,22 @@ epub_title = project # A list of files that should not be packed into the epub file. epub_exclude_files = ['search.html'] + +# ======== +# Headings +# ======== +# +# Headings +# ======== +# +# Heading 3 +# --------- +# +# Heading 4 +# ^^^^^^^^^ +# +# Heading 5 +# ~~~~~~~~~ +# +# Heading 6 +# ********* diff --git a/docs/source/tutorials/getting_started/shell_shortcuts.rst b/docs/source/tutorials/getting_started/shell_shortcuts.rst index 0c32d3fa4..cb5d01bdc 100644 --- a/docs/source/tutorials/getting_started/shell_shortcuts.rst +++ b/docs/source/tutorials/getting_started/shell_shortcuts.rst @@ -1,17 +1,18 @@ -OpenFPGA shortcuts ------------------- +OpenFPGA Shell Commands +----------------------- -OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh`` +OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh``, .. code-block:: bash + export OPENFPGA_PATH= cd ${OPENFPGA_PATH} && source openfpga.sh .. note:: The OpenFPGA shortcut works with only a bash-like shell. e.g., `bash`/`zsh`/`fish,` etc. -Shortcut Commands -^^^^^^^^^^^^^^^^^ +Commands +^^^^^^^^ Once the ``openfpga.sh`` script is sourced, you can run any following commands directly in the terminal. @@ -38,13 +39,21 @@ Once the ``openfpga.sh`` script is sourced, you can run any following commands d for example ``create-task _my_task_copy basic_tests/generate_fabric`` create a copy of the ``basic_tests/generate_fabric`` task in the current directory with ``_my_task_copy`` name. -.. option:: run-modelsim +.. option:: goto_task + + This command navigate shell to specific run-directory of the given task. + For example `goto_task lab1 2` will change directory to `run002` runt directory of `lab2` + +.. option:: clear-task-run + + Clears all run diretories of the given task + +.. option:: run-modelsim This command runs the verification using ModelSim. The test benches are generated during the OpenFPGA run. **Note**: users need to have ``VSIM`` installed and configured - .. option:: run-regression-local This script runs the regression test locally using the current version of OpenFPGA. diff --git a/openfpga.sh b/openfpga.sh index 81a6279ad..787fe5c88 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -41,15 +41,15 @@ create-task () { return fi template="template_tasks/yosys_vpr_template" - if [ ${#2} -ge 1 ]; then + if [ ${#2} -ge 1 ]; then if [[ "$2" == "vpr_blif" ]]; then template="template_tasks/${2}_template/"; - elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/"; - elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/"; - else template="$2" + elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/"; + elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/"; + else template="$2" fi fi - if [ ! -f $OPENFPGA_PATH/openfpga_flow/tasks/${template}/config/task.conf ]; then - echo "Template project [${template}] does not exist" ; return; + if [ ! -f $OPENFPGA_PATH/openfpga_flow/tasks/${template}/config/task.conf ]; then + echo "Template project [${template}] does not exist" ; return; fi echo "Creating task $1" echo "Template project ${template}" @@ -57,6 +57,11 @@ create-task () { cp -r $OPENFPGA_PATH/openfpga_flow/tasks/${template}/* $1/ } +rerun-task () { + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" +} + run-task () { $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" } @@ -66,7 +71,7 @@ clean-run () { } clear-task-run () { - $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all } run-modelsim () { diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf new file mode 100644 index 000000000..0d4e82645 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/vtr_benchmark_template_script.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/openfpga_arch.xml +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/k6_N10_tileable.xml +arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable.xml + +[BENCHMARKS] +bench1=${PATH:BENCH_PATH}/vtr_benchmark/ch_intrinsics.v +bench2=${PATH:BENCH_PATH}/vtr_benchmark/diffeq1.v +bench3=${PATH:BENCH_PATH}/vtr_benchmark/diffeq2.v +bench4=${PATH:BENCH_PATH}/vtr_benchmark/sha.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys + +# Benchmark top_module name +bench1_top = memset +bench2_top = diffeq_paj_convert +bench3_top = diffeq_f_systemC +bench4_top = sha1 + +[SCRIPT_PARAM_] +# + +[DEFAULT_PARSE_RESULT_VPR] +01_lut6_use = "lut6 : ([0-9]+)", int +02_lut5_use = "lut5 : ([0-9]+)", int \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml new file mode 100644 index 000000000..2b8b06cb3 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml new file mode 100644 index 000000000..27084cccf --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml @@ -0,0 +1,245 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/openfpga_arch.xml new file mode 100644 index 000000000..b045a0c39 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/openfpga_arch.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga new file mode 100644 index 000000000..ebe778df6 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga @@ -0,0 +1,7 @@ +# Execute VPR for architecture exploration + +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \ + --constant_net_method route + +exit \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml index 5af28d265..0fc9d794c 100644 --- a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml @@ -1,287 +1,191 @@ - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + --> + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf b/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf index f3a65f25d..22f0358a3 100644 --- a/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf @@ -13,25 +13,29 @@ power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 -# fpga_flow= vpr_blif If input in in .blif format -# fpga_flow= yosys_vpr If input in in .v format -fpga_flow=vpr_blif +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:TASK_DIR}/example_script.openfpga openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.blif +bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.v +bench1=${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v [SYNTHESIS_PARAM] +# Yosys script parameters +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys + bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and2/and2.v +bench1_top = mult8 +bench1_verilog = ${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga index a31f81948..d34090f36 100644 --- a/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml @@ -44,6 +44,7 @@ build_fabric_bitstream --verbose # Write fabric-dependent bitstream write_fabric_bitstream --file fabric_bitstream.bit --format plain_text +write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,9 +56,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v new file mode 100644 index 000000000..1ad0c1f19 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 8-bit combinational multiply circuit +//------------------------------------------------------- + +module mult8(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, + b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7, + out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, + out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15); +input a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7; +input b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7; +output out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7; +output out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15; + + assign a = {a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7}; + assign b = {b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7}; + assign out = {out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15}; + + assign out = a*b; + +endmodule + + diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml index 0ff0edfd3..db45d6d42 100644 --- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml @@ -1,11 +1,3 @@ - @@ -157,21 +149,18 @@ - + + + + + + + + + - - - - - - - - - - - diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml index 6d875aa50..c60b48336 100644 --- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml @@ -1,199 +1,226 @@ - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file From b71a1014e88160793f20476881f1a916c985d005 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 18:29:21 -0700 Subject: [PATCH 24/52] renamed vpr_blif_template to fabric_verification_template --- .../arch/openfpga_arch.xml | 0 .../arch/vpr_arch.xml | 0 .../config/task.conf | 0 .../example_script.openfpga | 0 .../micro_benchmark/and2/and2.act | 0 .../micro_benchmark/and2/and2.blif | 0 .../micro_benchmark/and2/and2.eblif | 0 .../micro_benchmark/and2/and2.v | 0 .../micro_benchmark/and2/and2_frac_lut4_arith.eblif | 0 .../micro_benchmark/and2/and2_verific.blif | 0 .../micro_benchmark/blinking/blinking.v | 0 .../micro_benchmark/mult8/mult8.v | 0 12 files changed, 0 insertions(+), 0 deletions(-) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/arch/openfpga_arch.xml (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/arch/vpr_arch.xml (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/config/task.conf (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/example_script.openfpga (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/and2/and2.act (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/and2/and2.blif (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/and2/and2.eblif (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/and2/and2.v (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/and2/and2_frac_lut4_arith.eblif (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/and2/and2_verific.blif (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/blinking/blinking.v (100%) rename openfpga_flow/tasks/template_tasks/{vpr_blif_template => fabric_verification_template}/micro_benchmark/mult8/mult8.v (100%) diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/vpr_arch.xml similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/vpr_arch.xml diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf b/openfpga_flow/tasks/template_tasks/fabric_verification_template/config/task.conf similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/config/task.conf diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.act similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.act diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.eblif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.v diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_verific.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_verific.blif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/blinking/blinking.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/blinking/blinking.v diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/mult8/mult8.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/mult8/mult8.v From b2bdfb7475d2c6967340e1d6ed7eae29cf2d261a Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 18:32:06 -0700 Subject: [PATCH 25/52] Strip down task --- .../arch/openfpga_arch.xml | 14 +++----------- .../example_script.openfpga | 10 ---------- 2 files changed, 3 insertions(+), 21 deletions(-) diff --git a/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml index b045a0c39..0ffc95e49 100644 --- a/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml @@ -1,11 +1,3 @@ - @@ -182,9 +174,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga index d34090f36..3fac06b3f 100644 --- a/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga @@ -60,16 +60,6 @@ write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VE write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - # Finish and exit OpenFPGA exit From f7c710e95e9acea8d935ed729fec5d37387fde44 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 18:33:06 -0700 Subject: [PATCH 26/52] renamed yosys_vpr_template fabric_netlist_gen_template --- .../arch/openfpga_arch.xml | 0 .../arch/vpr_arch.xml | 0 .../config/task.conf | 0 .../example_script.openfpga | 0 .../micro_benchmark/and2/and2.act | 0 .../micro_benchmark/and2/and2.blif | 0 .../micro_benchmark/and2/and2.eblif | 0 .../micro_benchmark/and2/and2.v | 0 .../micro_benchmark/and2/and2_frac_lut4_arith.eblif | 0 .../micro_benchmark/and2/and2_verific.blif | 0 .../micro_benchmark/blinking/blinking.v | 0 11 files changed, 0 insertions(+), 0 deletions(-) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/arch/openfpga_arch.xml (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/arch/vpr_arch.xml (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/config/task.conf (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/example_script.openfpga (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/and2/and2.act (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/and2/and2.blif (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/and2/and2.eblif (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/and2/and2.v (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/and2/and2_frac_lut4_arith.eblif (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/and2/and2_verific.blif (100%) rename openfpga_flow/tasks/template_tasks/{yosys_vpr_template => fabric_netlist_gen_template}/micro_benchmark/blinking/blinking.v (100%) diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/openfpga_arch.xml similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/openfpga_arch.xml diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/vpr_arch.xml similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/vpr_arch.xml diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/config/task.conf similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/config/task.conf diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/example_script.openfpga similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/example_script.openfpga diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.act similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.act diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.eblif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.v diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_verific.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_verific.blif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/blinking/blinking.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/blinking/blinking.v From 4f6b8c09058acd2428be84736196a16a6dd77047 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 11 Feb 2023 22:11:06 -0700 Subject: [PATCH 27/52] Updated regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 9fc356b49..a8f6c82aa 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -203,8 +203,9 @@ run-task basic_tests/io_constraints/empty_pcf $@ run-task basic_tests/io_constraints/pcf_ql_style $@ echo -e "Testing project templates"; -run-task template_tasks/vpr_blif_template $@ -run-task template_tasks/yosys_vpr_template $@ +run-task template_tasks/fabric_netlist_gen_template $@ +run-task template_tasks/fabric_verification_template $@ +run-task template_tasks/frac-lut-arch-explore_template $@ run-task template_tasks/vtr_benchmarks_template $@ echo -e "Testing create tsk from template and run task" From 6c3767a499c955ff813075cf3309dcd96ae89773 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 12 Feb 2023 10:41:25 -0800 Subject: [PATCH 28/52] Updating docker file for binder --- Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 22d150d40..b10c68b15 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -FROM ghcr.io/lnis-uofu/openfpga-master:latest +FROM ghcr.io/lnis-uofu/openfpga-master:10ffa828 # Install node js USER root From 541116faf588191c3702ce7a5b373b7e0678ee39 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 12 Feb 2023 11:50:11 -0700 Subject: [PATCH 29/52] Updated docker image --- Dockerfile | 11 ++++++++++- openfpga.sh | 5 +++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/Dockerfile b/Dockerfile index b10c68b15..4c369edc1 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -FROM ghcr.io/lnis-uofu/openfpga-master:10ffa828 +FROM ghcr.io/lnis-uofu/openfpga-master:9e4936f9 # Install node js USER root @@ -6,10 +6,19 @@ RUN curl -sL https://deb.nodesource.com/setup_14.x | bash - RUN curl -fsSL https://code-server.dev/install.sh | sh RUN apt-get install -y nodejs RUN apt-get install tree + +# = = = = = = = VSCODE Extension installation = = = = = = = +# Python support in vscode RUN code-server --install-extension ms-python.python +# For CSV file alignment RUN code-server --install-extension mechatroner.rainbow-csv +# For VCD Viewer RUN code-server --install-extension wavetrace.wavetrace +# For XML Linting RUN code-server --install-extension dotjoshjohnson.xml +# For git graphs +RUN code-server --install-extension mhutchie.git-graph +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = RUN usermod -u 2000 openfpga_user RUN groupmod -g 2000 openfpga_user diff --git a/openfpga.sh b/openfpga.sh index 787fe5c88..8773c3b30 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -42,8 +42,9 @@ create-task () { fi template="template_tasks/yosys_vpr_template" if [ ${#2} -ge 1 ]; then - if [[ "$2" == "vpr_blif" ]]; then template="template_tasks/${2}_template/"; - elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/"; + if [[ "$2" == "fabric_netlist_gen" ]]; then template="template_tasks/${2}_template/"; + elif [[ "$2" == "fabric_verification" ]]; then template="template_tasks/${2}_template/"; + elif [[ "$2" == "frac-lut-arch-explore" ]]; then template="template_tasks/${2}_template/"; elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/"; else template="$2" fi From f27aaaa5ae8ed70bbdb2df0a48e87785790adca9 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 12 Feb 2023 12:01:40 -0700 Subject: [PATCH 30/52] Updated dockerfile version --- Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 4c369edc1..662426607 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -FROM ghcr.io/lnis-uofu/openfpga-master:9e4936f9 +FROM ghcr.io/lnis-uofu/openfpga-master:0678ee39 # Install node js USER root From cdf6f2a171725eb68d6bbd22af1aaac88d555772 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 12 Feb 2023 12:36:21 -0700 Subject: [PATCH 31/52] Added extensions to docker file --- Dockerfile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Dockerfile b/Dockerfile index 662426607..cab3e7d93 100644 --- a/Dockerfile +++ b/Dockerfile @@ -13,11 +13,14 @@ RUN code-server --install-extension ms-python.python # For CSV file alignment RUN code-server --install-extension mechatroner.rainbow-csv # For VCD Viewer +RUN wget -O _wavetrace.gz https://marketplace.visualstudio.com/_apis/public/gallery/publishers/wavetrace/vsextensions/wavetrace/1.1.2/vspackage RUN code-server --install-extension wavetrace.wavetrace # For XML Linting RUN code-server --install-extension dotjoshjohnson.xml # For git graphs RUN code-server --install-extension mhutchie.git-graph +# verilog-linter +RUN code-server --install-extension mshr-h.veriloghdl # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = RUN usermod -u 2000 openfpga_user From 7c1f8cd746975223244597c3d0ee100ed1a6d216 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 12 Feb 2023 12:36:53 -0700 Subject: [PATCH 32/52] Updated docker version --- Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index cab3e7d93..0c7500540 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -FROM ghcr.io/lnis-uofu/openfpga-master:0678ee39 +FROM ghcr.io/lnis-uofu/openfpga-master:8d555772 # Install node js USER root From 23052f35edea8c408b6369f45fcc5c71121349b7 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 13 Feb 2023 00:02:16 +0000 Subject: [PATCH 33/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index c66d1fd16..e6d4990a0 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.706 +1.2.723 From ce4f30353dadf4d7efaf983772b2776a8e7c3e5b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 14 Feb 2023 08:00:43 +0000 Subject: [PATCH 34/52] Bump yosys-plugins from `08430ec` to `345fe14` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `08430ec` to `345fe14`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/08430ec4f53d1cf9d6a2091211d6c5ce501d5486...345fe14ee26f9de64170fffb00d7229ac6fe1864) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 08430ec4f..345fe14ee 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 08430ec4f53d1cf9d6a2091211d6c5ce501d5486 +Subproject commit 345fe14ee26f9de64170fffb00d7229ac6fe1864 From 920ac231f2d3ada92734608260b948bdf885c7ba Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 15 Feb 2023 00:02:29 +0000 Subject: [PATCH 35/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index e6d4990a0..146ba472d 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.723 +1.2.727 From 415982f7c49cf5222d5e737e3de35a75386e4a73 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 16 Feb 2023 07:58:43 +0000 Subject: [PATCH 36/52] Bump vtr-verilog-to-routing from `62e42cf` to `9e53e9a` Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `62e42cf` to `9e53e9a`. - [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases) - [Commits](https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/62e42cfbf7c4c0ddeb9ec79691a729a9afae1c5c...9e53e9a0a7c18ba9a16ea08678da726b98c669d4) --- updated-dependencies: - dependency-name: vtr-verilog-to-routing dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 62e42cfbf..9e53e9a0a 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 62e42cfbf7c4c0ddeb9ec79691a729a9afae1c5c +Subproject commit 9e53e9a0a7c18ba9a16ea08678da726b98c669d4 From f081a122042a831de5f3e56081d243062d216c8b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 17 Feb 2023 07:58:58 +0000 Subject: [PATCH 37/52] Bump yosys from `b1a0111` to `1cfedc9` Bumps [yosys](https://github.com/YosysHQ/yosys) from `b1a0111` to `1cfedc9`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/b1a011138ccc7ac840806d2a787f48f6baf6f107...1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index b1a011138..1cfedc90c 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit b1a011138ccc7ac840806d2a787f48f6baf6f107 +Subproject commit 1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7 From 81253ca48e0f6d63f32cc86d50d22bfbcc27726b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 17 Feb 2023 07:59:03 +0000 Subject: [PATCH 38/52] Bump yosys-plugins from `345fe14` to `43308c1` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `345fe14` to `43308c1`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/345fe14ee26f9de64170fffb00d7229ac6fe1864...43308c14324f88f59df758a575c12f55df90987f) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 345fe14ee..43308c143 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 345fe14ee26f9de64170fffb00d7229ac6fe1864 +Subproject commit 43308c14324f88f59df758a575c12f55df90987f From cea7892686d98505589eb21c053af419f711c0f9 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 19 Feb 2023 00:02:50 +0000 Subject: [PATCH 39/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 146ba472d..e197af3dd 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.727 +1.2.735 From f9475ee6e3f04dd32e351e72e5b1ad12c470c811 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 21 Feb 2023 07:58:32 +0000 Subject: [PATCH 40/52] Bump yosys from `1cfedc9` to `0f2d226` Bumps [yosys](https://github.com/YosysHQ/yosys) from `1cfedc9` to `0f2d226`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7...0f2d226ae971dc0b8de1be4514c49fbc5cfdbea2) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 1cfedc90c..0f2d226ae 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7 +Subproject commit 0f2d226ae971dc0b8de1be4514c49fbc5cfdbea2 From 08212a37196886dff4f31cb9a73da69d046d4cad Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 22 Feb 2023 00:02:38 +0000 Subject: [PATCH 41/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index e197af3dd..3bc202022 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.735 +1.2.739 From 9e3451e209ddaaaebf5112d21a09fa40064fa9f4 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 22 Feb 2023 07:18:32 +0000 Subject: [PATCH 42/52] Bump yosys-plugins from `43308c1` to `ae92491` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `43308c1` to `ae92491`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/43308c14324f88f59df758a575c12f55df90987f...ae92491a67fdbf77fb0c870b032edc6d3eded467) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 43308c143..ae92491a6 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 43308c14324f88f59df758a575c12f55df90987f +Subproject commit ae92491a67fdbf77fb0c870b032edc6d3eded467 From e9ff6d88f936ae04a657639435c33d926530bc19 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 23 Feb 2023 00:02:34 +0000 Subject: [PATCH 43/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 3bc202022..c2f6956a0 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.739 +1.2.743 From 6dba1d8a4793d8cb75a09b4a454b466df3049834 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 24 Feb 2023 07:19:49 +0000 Subject: [PATCH 44/52] Bump yosys from `0f2d226` to `8216b23` Bumps [yosys](https://github.com/YosysHQ/yosys) from `0f2d226` to `8216b23`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/0f2d226ae971dc0b8de1be4514c49fbc5cfdbea2...8216b23fb7b0ee1944403943eb066e0689129ba9) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 0f2d226ae..8216b23fb 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 0f2d226ae971dc0b8de1be4514c49fbc5cfdbea2 +Subproject commit 8216b23fb7b0ee1944403943eb066e0689129ba9 From 88af772588384f56ad6a7fcaafd7e9d555174025 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 26 Feb 2023 00:02:39 +0000 Subject: [PATCH 45/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index c2f6956a0..4d5eb4e04 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.743 +1.2.747 From c39356d3021748b629f2a9efea2e52c3b332ad04 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 1 Mar 2023 08:01:24 +0000 Subject: [PATCH 46/52] Bump yosys-plugins from `ae92491` to `ab3e14f` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ae92491` to `ab3e14f`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/ae92491a67fdbf77fb0c870b032edc6d3eded467...ab3e14fbc69bcc8f0575437b51a76d85f7d19c82) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index ae92491a6..ab3e14fbc 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit ae92491a67fdbf77fb0c870b032edc6d3eded467 +Subproject commit ab3e14fbc69bcc8f0575437b51a76d85f7d19c82 From eb5aa5f5ae021d555910a812d4adb75e66dcabed Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 2 Mar 2023 08:00:16 +0000 Subject: [PATCH 47/52] Bump yosys from `8216b23` to `9747e55` Bumps [yosys](https://github.com/YosysHQ/yosys) from `8216b23` to `9747e55`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/8216b23fb7b0ee1944403943eb066e0689129ba9...9747e55d9520631c4405ec42c02d5197c2ea57ab) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 8216b23fb..9747e55d9 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 8216b23fb7b0ee1944403943eb066e0689129ba9 +Subproject commit 9747e55d9520631c4405ec42c02d5197c2ea57ab From 0bdc9bab12e4bac056483e9e781ac4e6fda3ba13 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 4 Mar 2023 00:02:33 +0000 Subject: [PATCH 48/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 4d5eb4e04..68a3299b9 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.747 +1.2.753 From 3cb67c36eab7b9f47860c8b4d562e7b6854c7144 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 7 Mar 2023 07:59:59 +0000 Subject: [PATCH 49/52] Bump yosys-plugins from `ab3e14f` to `35a3c3c` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ab3e14f` to `35a3c3c`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/ab3e14fbc69bcc8f0575437b51a76d85f7d19c82...35a3c3c2e4e85d08cc40713346bb296f1a0e44d1) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index ab3e14fbc..35a3c3c2e 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit ab3e14fbc69bcc8f0575437b51a76d85f7d19c82 +Subproject commit 35a3c3c2e4e85d08cc40713346bb296f1a0e44d1 From 16c3c3b052b42d5a57dcbfc8d00af55cae55e12b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 7 Mar 2023 08:00:05 +0000 Subject: [PATCH 50/52] Bump yosys from `9747e55` to `b58664d` Bumps [yosys](https://github.com/YosysHQ/yosys) from `9747e55` to `b58664d`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/9747e55d9520631c4405ec42c02d5197c2ea57ab...b58664d441764b4de1d01c4efcdd45094ba71535) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 9747e55d9..b58664d44 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 9747e55d9520631c4405ec42c02d5197c2ea57ab +Subproject commit b58664d441764b4de1d01c4efcdd45094ba71535 From e973ea1ff54d7df7eb3eae1c7d35155752474939 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 8 Mar 2023 07:59:25 +0000 Subject: [PATCH 51/52] Bump yosys-plugins from `35a3c3c` to `24755e3` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `35a3c3c` to `24755e3`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/35a3c3c2e4e85d08cc40713346bb296f1a0e44d1...24755e3b43400ad25e90fe01cc764a28a12de999) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 35a3c3c2e..24755e3b4 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 35a3c3c2e4e85d08cc40713346bb296f1a0e44d1 +Subproject commit 24755e3b43400ad25e90fe01cc764a28a12de999 From 82c83d594e111bf95c190472b94e7d1467f0c93e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 9 Mar 2023 00:02:37 +0000 Subject: [PATCH 52/52] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 68a3299b9..f033f8ae0 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.753 +1.2.759