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[HDL] Add disclaimer for the frac_lut4_arith HDL codes

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tangxifan 2021-02-10 14:50:11 -07:00
parent 1c4dc9f74b
commit e683e00032
1 changed files with 5 additions and 1 deletions
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openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v
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@ -5,6 +5,10 @@
// - mode_bit[0] switch between arithmetic mode and LUT mode // - mode_bit[0] switch between arithmetic mode and LUT mode
// - mode_bit[1] switch between regular LUT mode and fracturable // - mode_bit[1] switch between regular LUT mode and fracturable
// mode // mode
// Note : The HDL is a technology mapped netlist based on the Skywater
// 130nm High-Density cell library.
// TODO: Create a behavioral HDL version so that we are portable
// between PDKs
// Coder : Xifan TANG // Coder : Xifan TANG
//----------------------------------------------------- //-----------------------------------------------------
module frac_lut4_arith ( module frac_lut4_arith (