From e683e0003238a01908b9df5082950166947a3a54 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Feb 2021 14:50:11 -0700 Subject: [PATCH] [HDL] Add disclaimer for the frac_lut4_arith HDL codes --- .../openfpga_cell_library/verilog/frac_lut4_arith.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v b/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v index 9a5af98af..0b5461615 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v @@ -5,6 +5,10 @@ // - mode_bit[0] switch between arithmetic mode and LUT mode // - mode_bit[1] switch between regular LUT mode and fracturable // mode +// Note : The HDL is a technology mapped netlist based on the Skywater +// 130nm High-Density cell library. +// TODO: Create a behavioral HDL version so that we are portable +// between PDKs // Coder : Xifan TANG //----------------------------------------------------- module frac_lut4_arith ( @@ -267,4 +271,4 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; .X(sky130_fd_sc_hd__mux2_1_14_X[0])); endmodule -// ----- END Verilog module for frac_lut4_mux ----- \ No newline at end of file +// ----- END Verilog module for frac_lut4_mux -----