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fix bugs for wired LUTs

This commit is contained in:
tangxifan 2018-11-27 12:46:30 -07:00
parent de2bc18bbb
commit e223868df8
10 changed files with 167 additions and 77 deletions
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59
vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c
View File

@ -5844,6 +5844,54 @@ void get_logical_block_output_vpack_net_num(t_logical_block* cur_logical_block,
return;
}
int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node,
t_rr_node* op_pb_rr_graph) {
int iport, ipin;
int wired_lut_lb_index = OPEN;
int num_used_lut_input_pins = 0;
int num_used_lut_output_pins = 0;
int temp_rr_node_index;
int lut_output_vpack_net_num = OPEN;
num_used_lut_input_pins = 0;
/* Find the used input pin of this LUT and rr_node in the graph */
for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) {
for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) {
temp_rr_node_index = cur_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster;
if (OPEN != op_pb_rr_graph[temp_rr_node_index].vpack_net_num) {
num_used_lut_input_pins++;
lut_output_vpack_net_num = op_pb_rr_graph[temp_rr_node_index].vpack_net_num;
}
}
}
/* Make sure we only have 1 used input pin */
assert ((1 == num_used_lut_input_pins)
&& (OPEN != lut_output_vpack_net_num));
/* vpr_printf(TIO_MESSAGE_INFO, "Wired LUT output vpack_net_num is %d\n", lut_output_vpack_net_num); */
/* Find the used output*/
num_used_lut_output_pins = 0;
/* Find the used output pin of this LUT and rr_node in the graph */
for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) {
for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) {
temp_rr_node_index = cur_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster;
if (lut_output_vpack_net_num == op_pb_rr_graph[temp_rr_node_index].vpack_net_num) { /* TODO: Shit... I do not why the vpack_net_num is not synchronized to the net_num !!! */
num_used_lut_output_pins++;
}
}
}
/* Make sure we only have 1 used output pin */
/* vpr_printf(TIO_MESSAGE_INFO, "Wired LUT num_used_lut_output_pins is %d\n", num_used_lut_output_pins); */
assert (1 == num_used_lut_output_pins);
/* The logical block is the driver for this vpack_net( node_block[0] )*/
wired_lut_lb_index = vpack_net[lut_output_vpack_net_num].node_block[0];
assert (OPEN != wired_lut_lb_index);
return wired_lut_lb_index;
}
/* Adapt the truth from the actual connection from the input nets of a LUT,
*/
@ -7505,21 +7553,22 @@ boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,
}
/* Get the vpack_net_num of all the input pins of a LUT physical pb */
void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb,
void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb_graph_node* lut_pb_graph_node,
t_rr_node* pb_rr_graph,
int* num_lut_pin, int** lut_pin_net) {
int ipin, inode;
/* Check */
assert (1 == lut_pb->pb_graph_node->num_input_ports);
(*num_lut_pin) = lut_pb->pb_graph_node->num_input_pins[0];
assert (1 == lut_pb_graph_node->num_input_ports);
(*num_lut_pin) = lut_pb_graph_node->num_input_pins[0];
/* Allocate */
(*lut_pin_net) = (int*) my_malloc ((*num_lut_pin) * sizeof(int));
/* Fill the array */
for (ipin = 0; ipin < (*num_lut_pin); ipin++) {
inode = lut_pb->pb_graph_node->input_pins[0][ipin].pin_count_in_cluster;
(*lut_pin_net)[ipin] = lut_pb->rr_graph[inode].vpack_net_num;
inode = lut_pb_graph_node->input_pins[0][ipin].pin_count_in_cluster;
(*lut_pin_net)[ipin] = pb_rr_graph[inode].vpack_net_num;
}
return;

6
vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.h
View File

@ -461,6 +461,9 @@ void get_logical_block_output_vpack_net_num(t_logical_block* cur_logical_block,
int* num_lb_output_ports, int** num_lb_output_pins,
int*** lb_output_vpack_net_num);
int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node,
t_rr_node* op_pb_rr_graph);
char** assign_post_routing_wired_lut_truth_table(t_logical_block* wired_lut_logical_block,
int lut_size, int* lut_pin_vpack_net_num,
int* truth_table_length);
@ -644,7 +647,8 @@ t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head,
boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,
char* subckt_file_name);
void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb,
void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb_graph_node* lut_pb_graph_node,
t_rr_node* pb_rr_graph,
int* num_lut_pin, int** lut_pin_net);
void rec_stats_spice_model_global_ports(t_spice_model* cur_spice_model,

19
vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c
View File

@ -178,7 +178,8 @@ void fprint_pb_primitive_lut(FILE* fp,
t_pb_graph_node* cur_pb_graph_node,
int index,
t_spice_model* spice_model,
int lut_status) {
int lut_status,
t_rr_node* pb_rr_graph) {
int i;
int num_sram = 0;
int* sram_bits = NULL; /* decoded SRAM bits */
@ -220,17 +221,25 @@ void fprint_pb_primitive_lut(FILE* fp,
/* Check if this is an idle logical block mapped*/
switch (lut_status) {
case PRIMITIVE_WIRED_LUT:
assert(NULL != pb_rr_graph);
if (NULL == mapped_logical_block) {
break; /* Jump out if there is no mapped logical block */
}
/* Get the mapped vpack_net_num of this physical LUT pb */
get_mapped_lut_pb_input_pin_vpack_net_num(cur_pb_graph_node, pb_rr_graph, &num_lut_pin_nets, &lut_pin_net);
/* consider LUT pin remapping when assign lut truth tables */
mapped_logical_block = &logical_block[get_pb_graph_node_wired_lut_logical_block_index(cur_pb_graph_node, pb_rr_graph)];
/* Match truth table and post-routing results */
truth_table = assign_post_routing_wired_lut_truth_table(mapped_logical_block,
num_lut_pin_nets, lut_pin_net, &truth_table_length);
} else {
/* Give a special truth table */
assert (VPACK_COMB == mapped_logical_block->type);
/* Get the mapped vpack_net_num of this physical LUT pb */
get_mapped_lut_pb_input_pin_vpack_net_num(prim_pb, &num_lut_pin_nets, &lut_pin_net);
get_mapped_lut_pb_input_pin_vpack_net_num(cur_pb_graph_node, pb_rr_graph, &num_lut_pin_nets, &lut_pin_net);
/* consider LUT pin remapping when assign lut truth tables */
/* Match truth table and post-routing results */
truth_table = assign_post_routing_wired_lut_truth_table(mapped_logical_block,
num_lut_pin_nets, lut_pin_net, &truth_table_length);
}
break;
case PRIMITIVE_IDLE:
break;
@ -243,7 +252,7 @@ void fprint_pb_primitive_lut(FILE* fp,
assert (VPACK_COMB == mapped_logical_block->type);
/* Get the mapped vpack_net_num of this physical LUT pb */
get_mapped_lut_pb_input_pin_vpack_net_num(prim_pb, &num_lut_pin_nets, &lut_pin_net);
get_mapped_lut_pb_input_pin_vpack_net_num(cur_pb_graph_node, pb_rr_graph, &num_lut_pin_nets, &lut_pin_net);
/* consider LUT pin remapping when assign lut truth tables */
/* Match truth table and post-routing results */
truth_table = assign_post_routing_lut_truth_table(mapped_logical_block,

3
vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.h
View File

@ -16,4 +16,5 @@ void fprint_pb_primitive_lut(FILE* fp,
t_pb_graph_node* cur_pb_graph_node,
int index,
t_spice_model* spice_model,
int lut_status);
int lut_status,
t_rr_node* pb_rr_graph);

38
vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_pbtypes.c
View File

@ -970,7 +970,8 @@ void fprint_pb_primitive_spice_model(FILE* fp,
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* spice_model,
int is_idle) {
int is_idle,
t_rr_node* pb_rr_graph) {
t_pb_type* prim_pb_type = NULL;
t_logical_block* mapped_logical_block = NULL;
@ -1037,7 +1038,7 @@ void fprint_pb_primitive_spice_model(FILE* fp,
case SPICE_MODEL_LUT:
/* If this is a idle block we should set sram_bits to zero*/
fprint_pb_primitive_lut(fp, subckt_prefix, prim_pb, mapped_logical_block, prim_pb_graph_node,
pb_index, spice_model, is_idle);
pb_index, spice_model, is_idle, pb_rr_graph);
break;
case SPICE_MODEL_FF:
assert(NULL != spice_model->model_netlist);
@ -1121,7 +1122,7 @@ void fprint_spice_idle_pb_graph_node_rec(FILE* fp,
if (NULL != cur_pb_type->spice_model) {
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 1);
pb_type_index, cur_pb_type->spice_model, 1, NULL);
/* Finish the primitive node, we return */
return;
}
@ -1233,7 +1234,8 @@ void fprint_spice_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,
t_pb* cur_pb,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index) {
int pb_type_index,
t_rr_node* pb_rr_graph) {
int mode_index, ipb, jpb, child_mode_index;
t_pb_type* cur_pb_type = NULL;
char* subckt_name = NULL;
@ -1264,7 +1266,7 @@ void fprint_spice_pb_graph_node_rec(FILE* fp,
assert (LUT_CLASS == cur_pb_type->class_type);
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, PRIMITIVE_WIRED_LUT);
pb_type_index, cur_pb_type->spice_model, PRIMITIVE_WIRED_LUT, pb_rr_graph);
return;
}
@ -1287,7 +1289,7 @@ void fprint_spice_pb_graph_node_rec(FILE* fp,
/* Refer to pack/output_clustering.c [LINE 392] */
if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) {
fprint_spice_pb_graph_node_rec(fp, pass_on_prefix, &(cur_pb->child_pbs[ipb][jpb]),
cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb);
cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb, cur_pb->rr_graph);
/* For wired LUT */
} else if (TRUE == is_pb_wired_lut(&(cur_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]),
&(cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb]),
@ -1297,7 +1299,7 @@ void fprint_spice_pb_graph_node_rec(FILE* fp,
*/
fprint_spice_pb_graph_node_rec(fp, pass_on_prefix, NULL,
&(cur_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]),
jpb);
jpb, cur_pb->rr_graph);
} else {
/* Check if this pb has no children, no children mean idle*/
fprint_spice_idle_pb_graph_node_rec(fp, pass_on_prefix,
@ -1319,27 +1321,27 @@ void fprint_spice_pb_graph_node_rec(FILE* fp,
child_pb = get_lut_child_pb(cur_pb, mode_index);
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
child_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, child_pb->rr_graph);
break;
case LATCH_CLASS:
assert(0 == cur_pb_type->num_modes);
/* Consider the num_pb, create all the subckts*/
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, cur_pb->rr_graph);
break;
case MEMORY_CLASS:
child_pb = get_hardlogic_child_pb(cur_pb, mode_index);
/* Consider the num_pb, create all the subckts*/
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
child_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, child_pb->rr_graph);
break;
case UNKNOWN_CLASS:
/* Consider the num_pb, create all the subckts*/
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, cur_pb->rr_graph);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n",
@ -1450,6 +1452,7 @@ void fprint_spice_phy_pb_graph_node_rec(FILE* fp,
char* subckt_port_prefix = NULL;
t_pb* child_pb = NULL;
t_rr_node* pb_rr_graph = NULL;
/* Check the file handler*/
if (NULL == fp) {
@ -1468,6 +1471,9 @@ void fprint_spice_phy_pb_graph_node_rec(FILE* fp,
is_idle = 1;
if (NULL != cur_pb) {
is_idle = 0;
pb_rr_graph = cur_pb->rr_graph;
} else {
pb_rr_graph = NULL;
}
/* Recursively finish all the child pb_types*/
@ -1504,7 +1510,7 @@ void fprint_spice_phy_pb_graph_node_rec(FILE* fp,
if (1 == is_idle) {
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, is_idle);
pb_type_index, cur_pb_type->spice_model, is_idle, NULL);
} else {
child_pb = get_lut_child_pb(cur_pb, mode_index);
/* Special care for LUT !!!
@ -1512,7 +1518,7 @@ void fprint_spice_phy_pb_graph_node_rec(FILE* fp,
*/
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
child_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, is_idle);
pb_type_index, cur_pb_type->spice_model, is_idle, child_pb->rr_graph);
}
break;
case LATCH_CLASS:
@ -1520,14 +1526,14 @@ void fprint_spice_phy_pb_graph_node_rec(FILE* fp,
/* Consider the num_pb, create all the subckts*/
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, is_idle);
pb_type_index, cur_pb_type->spice_model, is_idle, pb_rr_graph);
break;
case UNKNOWN_CLASS:
case MEMORY_CLASS:
/* Consider the num_pb, create all the subckts*/
fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, is_idle);
pb_type_index, cur_pb_type->spice_model, is_idle, pb_rr_graph);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n",
@ -1647,7 +1653,7 @@ void fprint_spice_block(FILE* fp,
* Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined.
* The index of such top pb_type is always 0.
*/
fprint_spice_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z);
fprint_spice_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z, top_pb->rr_graph);
return;
}

6
vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_pbtypes.h
View File

@ -48,7 +48,8 @@ void fprint_pb_primitive_spice_model(FILE* fp,
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* spice_model,
int is_idle);
int is_idle,
t_rr_node* pb_rr_graph);
void fprint_spice_idle_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,
@ -59,7 +60,8 @@ void fprint_spice_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,
t_pb* cur_pb,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index);
int pb_type_index,
t_rr_node* pb_rr_graph);
void fprint_spice_block(FILE* fp,

19
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c
View File

@ -40,7 +40,8 @@ void dump_verilog_pb_primitive_lut(FILE* fp,
t_pb_graph_node* cur_pb_graph_node,
int index,
t_spice_model* verilog_model,
int lut_status) {
int lut_status,
t_rr_node* pb_rr_graph) {
int i;
int* sram_bits = NULL; /* decoded SRAM bits */
int truth_table_length = 0;
@ -98,17 +99,25 @@ void dump_verilog_pb_primitive_lut(FILE* fp,
/* Check if this is an idle logical block mapped*/
switch (lut_status) {
case PRIMITIVE_WIRED_LUT:
assert(NULL != pb_rr_graph);
if (NULL == mapped_logical_block) {
break; /* Jump out if there is no mapped logical block */
}
/* Get the mapped vpack_net_num of this physical LUT pb */
get_mapped_lut_pb_input_pin_vpack_net_num(cur_pb_graph_node, pb_rr_graph, &num_lut_pin_nets, &lut_pin_net);
/* consider LUT pin remapping when assign lut truth tables */
mapped_logical_block = &logical_block[get_pb_graph_node_wired_lut_logical_block_index(cur_pb_graph_node, pb_rr_graph)];
/* Match truth table and post-routing results */
truth_table = assign_post_routing_wired_lut_truth_table(mapped_logical_block,
num_lut_pin_nets, lut_pin_net, &truth_table_length);
} else {
/* Give a special truth table */
assert (VPACK_COMB == mapped_logical_block->type);
/* Get the mapped vpack_net_num of this physical LUT pb */
get_mapped_lut_pb_input_pin_vpack_net_num(prim_pb, &num_lut_pin_nets, &lut_pin_net);
get_mapped_lut_pb_input_pin_vpack_net_num(cur_pb_graph_node, pb_rr_graph, &num_lut_pin_nets, &lut_pin_net);
/* consider LUT pin remapping when assign lut truth tables */
/* Match truth table and post-routing results */
truth_table = assign_post_routing_wired_lut_truth_table(mapped_logical_block,
num_lut_pin_nets, lut_pin_net, &truth_table_length);
}
break;
case PRIMITIVE_IDLE:
break;
@ -120,7 +129,7 @@ void dump_verilog_pb_primitive_lut(FILE* fp,
assert (VPACK_COMB == mapped_logical_block->type);
/* Get the mapped vpack_net_num of this physical LUT pb */
get_mapped_lut_pb_input_pin_vpack_net_num(prim_pb, &num_lut_pin_nets, &lut_pin_net);
get_mapped_lut_pb_input_pin_vpack_net_num(cur_pb_graph_node, pb_rr_graph, &num_lut_pin_nets, &lut_pin_net);
/* consider LUT pin remapping when assign lut truth tables */
/* Match truth table and post-routing results */
truth_table = assign_post_routing_lut_truth_table(mapped_logical_block,

3
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.h
View File

@ -6,4 +6,5 @@ void dump_verilog_pb_primitive_lut(FILE* fp,
t_pb_graph_node* cur_pb_graph_node,
int index,
t_spice_model* spice_model,
int lut_status);
int lut_status,
t_rr_node* pb_rr_graph);

43
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c
View File

@ -1579,7 +1579,8 @@ void dump_verilog_pb_primitive_verilog_model(FILE* fp,
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* verilog_model,
int is_idle) {
int is_idle,
t_rr_node* pb_rr_graph) {
t_pb_type* prim_pb_type = NULL;
t_logical_block* mapped_logical_block = NULL;
@ -1645,7 +1646,7 @@ void dump_verilog_pb_primitive_verilog_model(FILE* fp,
case SPICE_MODEL_LUT:
/* If this is a idle block we should set sram_bits to zero*/
dump_verilog_pb_primitive_lut(fp, subckt_prefix, prim_pb, mapped_logical_block, prim_pb_graph_node,
pb_index, verilog_model, is_idle);
pb_index, verilog_model, is_idle, pb_rr_graph);
break;
case SPICE_MODEL_FF:
assert(NULL != verilog_model->model_netlist);
@ -1749,7 +1750,7 @@ void dump_verilog_idle_pb_graph_node_rec(FILE* fp,
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model, 1);
cur_pb_type->spice_model, 1, NULL);
/* update the number of SRAM, I/O pads */
stamped_sram_cnt += cur_pb_type->default_mode_num_conf_bits;
break;
@ -1757,7 +1758,7 @@ void dump_verilog_idle_pb_graph_node_rec(FILE* fp,
assert(0 == cur_pb_type->num_modes);
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 1);
NULL, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 1, NULL);
/* update the number of SRAM, I/O pads */
/* update stamped sram counter */
stamped_sram_cnt += cur_pb_type->default_mode_num_conf_bits;
@ -1766,7 +1767,7 @@ void dump_verilog_idle_pb_graph_node_rec(FILE* fp,
case MEMORY_CLASS:
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 1);
NULL, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 1, NULL);
/* update the number of SRAM, I/O pads */
/* update stamped sram counter */
stamped_sram_cnt += cur_pb_type->default_mode_num_conf_bits;
@ -1948,7 +1949,8 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,
t_pb* cur_pb,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index) {
int pb_type_index,
t_rr_node* pb_rr_graph) {
int mode_index, ipb, jpb, child_mode_index;
t_pb_type* cur_pb_type = NULL;
char* subckt_name = NULL;
@ -1990,7 +1992,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
assert (LUT_CLASS == cur_pb_type->class_type);
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, PRIMITIVE_WIRED_LUT);
pb_type_index, cur_pb_type->spice_model, PRIMITIVE_WIRED_LUT, pb_rr_graph);
/* update the number of SRAM, I/O pads */
/* update stamped iopad counter */
/* stamped_iopad_cnt += cur_pb->num_iopads; */
@ -2023,7 +2025,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
/* Refer to pack/output_clustering.c [LINE 392] */
if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) {
dump_verilog_pb_graph_node_rec(fp, pass_on_prefix, &(cur_pb->child_pbs[ipb][jpb]),
cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb);
cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb , cur_pb->rr_graph);
/* For wired LUT */
} else if (TRUE == is_pb_wired_lut(&(cur_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]),
&(cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb]),
@ -2033,7 +2035,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
*/
dump_verilog_pb_graph_node_rec(fp, pass_on_prefix, NULL,
&(cur_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]),
jpb);
jpb, cur_pb->rr_graph);
} else {
/* Check if this pb has no children, no children mean idle*/
dump_verilog_idle_pb_graph_node_rec(fp, pass_on_prefix,
@ -2052,7 +2054,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
child_pb = get_lut_child_pb(cur_pb, mode_index);
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
child_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, child_pb->rr_graph);
/* update the number of SRAM, I/O pads */
/* update stamped iopad counter */
stamped_iopad_cnt += cur_pb->num_iopads;
@ -2064,7 +2066,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, cur_pb->rr_graph);
/* update the number of SRAM, I/O pads */
/* update stamped iopad counter */
stamped_iopad_cnt += cur_pb->num_iopads;
@ -2076,7 +2078,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
child_pb, cur_pb_graph_node,
pb_type_index, cur_pb_type->spice_model, 0);
pb_type_index, cur_pb_type->spice_model, 0, cur_pb->rr_graph);
/* update the number of SRAM, I/O pads */
/* update stamped iopad counter */
stamped_iopad_cnt += cur_pb->num_iopads;
@ -2086,7 +2088,7 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
case UNKNOWN_CLASS:
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 0);
cur_pb, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 0, cur_pb->rr_graph);
/* update the number of SRAM, I/O pads */
/* update stamped iopad counter */
stamped_iopad_cnt += cur_pb->num_iopads;
@ -2298,6 +2300,8 @@ void dump_verilog_phy_pb_graph_node_rec(FILE* fp,
int stamped_iopad_cnt = iopad_verilog_model->cnt;
t_rr_node* pb_rr_graph = NULL;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -2316,6 +2320,9 @@ void dump_verilog_phy_pb_graph_node_rec(FILE* fp,
is_idle = 1;
if (NULL != cur_pb) {
is_idle = 0;
pb_rr_graph = cur_pb->rr_graph;
} else {
pb_rr_graph = NULL;
}
/* Recursively finish all the child pb_types*/
@ -2352,7 +2359,7 @@ void dump_verilog_phy_pb_graph_node_rec(FILE* fp,
if (1 == is_idle) {
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
NULL, cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model, is_idle); /* last param means idle */
cur_pb_type->spice_model, is_idle, NULL); /* last param means idle */
} else {
child_pb = get_lut_child_pb(cur_pb, mode_index);
/* Special care for LUT !!!
@ -2360,21 +2367,21 @@ void dump_verilog_phy_pb_graph_node_rec(FILE* fp,
*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
child_pb, cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model, is_idle); /* last param means idle */
cur_pb_type->spice_model, is_idle, child_pb->rr_graph); /* last param means idle */
}
case LATCH_CLASS:
assert(0 == cur_pb_type->num_modes);
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model, is_idle); /* last param means idle */
cur_pb_type->spice_model, is_idle, pb_rr_graph); /* last param means idle */
break;
case UNKNOWN_CLASS:
case MEMORY_CLASS:
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix,
cur_pb, cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model, is_idle); /* last param means idle */
cur_pb_type->spice_model, is_idle, pb_rr_graph); /* last param means idle */
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n",
@ -2588,7 +2595,7 @@ void dump_verilog_block(FILE* fp,
* Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined.
* The index of such top pb_type is always 0.
*/
dump_verilog_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z);
dump_verilog_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z, top_pb->rr_graph);
return;
}

8
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.h
View File

@ -70,13 +70,14 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index);
void dump_pb_primitive_verilog_model(FILE* fp,
void dump_verilog_pb_primitive_verilog_model(FILE* fp,
char* subckt_prefix,
t_pb* prim_pb,
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* verilog_model,
int is_idle);
int is_idle,
t_rr_node* pb_rr_graph);
void dump_verilog_idle_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,
@ -87,7 +88,8 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,
t_pb* cur_pb,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index);
int pb_type_index,
t_rr_node* pb_rr_graph);
void dump_verilog_phy_pb_graph_node_rec(FILE* fp,
char* subckt_prefix,