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[Test] Deploy synthesizable verilog test to CI

This commit is contained in:
tangxifan 2021-02-17 16:13:15 -07:00
parent e19fc15fec
commit e08ac1a41e
1 changed files with 3 additions and 0 deletions
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -95,6 +95,9 @@ run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
echo -e "Testing Verilog generation with behavioral description";
run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs
echo -e "Testing synthesizable Verilog generation with external standard cells";
run-task fpga_verilog/synthesizable_verilog --debug --show_thread_logs
echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/implicit_verilog --debug --show_thread_logs