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use constant string for inverted port naming

This commit is contained in:
tangxifan 2020-05-17 19:45:27 -06:00
parent c2a81c76e1
commit e089b0ef22
6 changed files with 17 additions and 10 deletions
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3
openfpga/src/base/openfpga_reserved_words.h
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@ -30,6 +30,9 @@ constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
/* Inverted port naming */
constexpr char* INV_PORT_POSTFIX = "_inv";
/* Bitstream file strings */ /* Bitstream file strings */
constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml"; constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";

7
openfpga/src/fabric/build_lut_modules.cpp
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@ -10,6 +10,7 @@
#include "vtr_log.h" #include "vtr_log.h"
#include "vtr_time.h" #include "vtr_time.h"
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h" #include "openfpga_naming.h"
#include "circuit_library_utils.h" #include "circuit_library_utils.h"
#include "module_manager.h" #include "module_manager.h"
@ -106,7 +107,7 @@ void build_lut_module(ModuleManager& module_manager,
for (const auto& port : lut_regular_sram_ports) { for (const auto& port : lut_regular_sram_ports) {
BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port)); BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX), circuit_lib.port_size(port));
module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
} }
@ -114,7 +115,7 @@ void build_lut_module(ModuleManager& module_manager,
for (const auto& port : lut_mode_select_sram_ports) { for (const auto& port : lut_mode_select_sram_ports) {
BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port)); BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX), circuit_lib.port_size(port));
module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
} }
@ -336,7 +337,7 @@ void build_lut_module(ModuleManager& module_manager,
module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin); module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin);
} }
ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + "_inv")); ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + INV_PORT_POSTFIX));
BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id); BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id);
VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size()); VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size());
/* Wire the port to lut_mux_sram_net */ /* Wire the port to lut_mux_sram_net */

6
openfpga/src/fabric/build_mux_modules.cpp
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@ -977,7 +977,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag
/* Add mem and mem_inv nets here */ /* Add mem and mem_inv nets here */
size_t mem_inv_net_cnt = 0; size_t mem_inv_net_cnt = 0;
for (const auto& port : mux_sram_ports) { for (const auto& port : mux_sram_ports) {
ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + "_inv")); ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX));
BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id); BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id);
for (const size_t& pin : mem_inv_port.pins()) { for (const size_t& pin : mem_inv_port.pins()) {
MuxMemId mem_id = MuxMemId(mem_inv_net_cnt); MuxMemId mem_id = MuxMemId(mem_inv_net_cnt);
@ -998,7 +998,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag
/* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */
ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0])); ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]));
ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + "_inv"); ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + INV_PORT_POSTFIX);
BasicPort lvl_addr_port(circuit_lib.port_prefix(mux_sram_ports[0]), 0); BasicPort lvl_addr_port(circuit_lib.port_prefix(mux_sram_ports[0]), 0);
BasicPort lvl_data_port(decoder_data_port.get_name(), 0); BasicPort lvl_data_port(decoder_data_port.get_name(), 0);
BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0);
@ -1181,7 +1181,7 @@ void build_cmos_mux_module(ModuleManager& module_manager,
for (const auto& port : mux_sram_ports) { for (const auto& port : mux_sram_ports) {
BasicPort mem_port(circuit_lib.port_prefix(port), num_mems); BasicPort mem_port(circuit_lib.port_prefix(port), num_mems);
module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), num_mems); BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX), num_mems);
module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
/* Update counter */ /* Update counter */
sram_port_cnt++; sram_port_cnt++;

3
openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
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@ -23,6 +23,7 @@
#include "openfpga_port.h" #include "openfpga_port.h"
#include "openfpga_digest.h" #include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h" #include "openfpga_naming.h"
#include "circuit_library_utils.h" #include "circuit_library_utils.h"
@ -87,7 +88,7 @@ int print_sdc_disable_lut_configure_ports(std::fstream& fp,
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }
const std::string& sram_inv_port_name = circuit_lib.port_lib_name(sram_port) + "_inv"; const std::string& sram_inv_port_name = circuit_lib.port_lib_name(sram_port) + INV_PORT_POSTFIX;
VTR_ASSERT(true == module_manager.valid_module_port_id(programmable_module, module_manager.find_module_port(programmable_module, sram_inv_port_name))); VTR_ASSERT(true == module_manager.valid_module_port_id(programmable_module, module_manager.find_module_port(programmable_module, sram_inv_port_name)));
if (CMD_EXEC_FATAL_ERROR == if (CMD_EXEC_FATAL_ERROR ==
rec_print_sdc_disable_timing_for_module_ports(fp, rec_print_sdc_disable_timing_for_module_ports(fp,

3
openfpga/src/fpga_sdc/sdc_mux_utils.cpp
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@ -14,6 +14,7 @@
/* Headers from openfpgautil library */ /* Headers from openfpgautil library */
#include "openfpga_digest.h" #include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h" #include "openfpga_naming.h"
#include "mux_utils.h" #include "mux_utils.h"
@ -147,7 +148,7 @@ int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }
const std::string& mux_sram_inv_port_name = circuit_lib.port_lib_name(mux_sram_port) + "_inv"; const std::string& mux_sram_inv_port_name = circuit_lib.port_lib_name(mux_sram_port) + INV_PORT_POSTFIX;
VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_inv_port_name))); VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_inv_port_name)));
if (CMD_EXEC_FATAL_ERROR == if (CMD_EXEC_FATAL_ERROR ==
rec_print_sdc_disable_timing_for_module_ports(fp, rec_print_sdc_disable_timing_for_module_ports(fp,

5
openfpga/src/utils/module_manager_utils.cpp
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@ -13,6 +13,7 @@
/* Headers from openfpgautil library */ /* Headers from openfpgautil library */
#include "openfpga_port.h" #include "openfpga_port.h"
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h" #include "openfpga_naming.h"
#include "memory_utils.h" #include "memory_utils.h"
#include "pb_type_utils.h" #include "pb_type_utils.h"
@ -612,11 +613,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
std::vector<std::string> logic_model_sramb_port_names; std::vector<std::string> logic_model_sramb_port_names;
/* Regular sram port goes first */ /* Regular sram port goes first */
for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) {
logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string("_inv")); logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string(INV_PORT_POSTFIX));
} }
/* Mode-select sram port goes first */ /* Mode-select sram port goes first */
for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) {
logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string("_inv")); logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string(INV_PORT_POSTFIX));
} }
/* Find the port ids in the memory */ /* Find the port ids in the memory */
std::vector<ModulePortId> logic_module_sramb_port_ids; std::vector<ModulePortId> logic_module_sramb_port_ids;