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[test] enable missing options in the arch used by benchmark sweeping tests

This commit is contained in:
tangxifan 2023-11-14 09:45:02 -08:00
parent 0b473e3454
commit dff03e7993
3 changed files with 3 additions and 3 deletions
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2
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
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@ -234,7 +234,7 @@
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true" through_channel="false">
<layout tileable="true" through_channel="false" concat_pass_wire="true">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>

2
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
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@ -302,7 +302,7 @@
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true" through_channel="false">
<layout tileable="true" through_channel="false" concat_pass_wire="true">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>

2
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
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@ -146,7 +146,7 @@
<!-- Apply tileable routing architecture.
This is strongly recommended if you want to PnR large FPGA fabric
-->
<layout tileable="true">
<layout tileable="true" concat_pass_wire="true">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>