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Bug fix for non fracturable LUT

This commit is contained in:
AurelienUoU 2019-08-14 09:32:15 -06:00
parent 30c0f2b6b7
commit df873903f8
1 changed files with 18 additions and 18 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
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@ -656,7 +656,6 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
}
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_out( ");
}
@ -676,6 +675,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
}
break;
case SPICE_SRAM_MEMORY_BANK:
if (TRUE == subckt_require_explicit_port_map) {