From df873903f8edb83d172fc40ec4ab4047adea9f28 Mon Sep 17 00:00:00 2001
From: AurelienUoU <u1235811@lnissrv4.eng.utah.edu>
Date: Wed, 14 Aug 2019 09:32:15 -0600
Subject: [PATCH] Bug fix for non fracturable LUT

---
 .../SRC/fpga_x2p/verilog/verilog_primitives.c | 36 +++++++++----------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
index 446897397..a487a5677 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
@@ -656,25 +656,25 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
     }
     if (0 < num_mode_sram) {
       fprintf(fp, ", ");
-    }
-    if (TRUE == subckt_require_explicit_port_map) {
-      fprintf(fp, ".mode_out( ");
-    }
-    dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 
-                                        cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 
-                                        0, VERILOG_PORT_CONKT);
-    if (TRUE == subckt_require_explicit_port_map) {
-      fprintf(fp, ")");
-    }
+      if (TRUE == subckt_require_explicit_port_map) {
+        fprintf(fp, ".mode_out( ");
+      }
+      dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 
+                                          cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 
+                                          0, VERILOG_PORT_CONKT);
+      if (TRUE == subckt_require_explicit_port_map) {
+        fprintf(fp, ")");
+      }
       fprintf(fp, ", ");
-    if (TRUE == subckt_require_explicit_port_map) {
-      fprintf(fp, ".mode_outb( ");
-    }
-    dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 
-                                        cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 
-                                        1, VERILOG_PORT_CONKT);
-    if (TRUE == subckt_require_explicit_port_map) {
-      fprintf(fp, ")");
+      if (TRUE == subckt_require_explicit_port_map) {
+        fprintf(fp, ".mode_outb( ");
+      }
+      dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 
+                                          cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 
+                                          1, VERILOG_PORT_CONKT);
+      if (TRUE == subckt_require_explicit_port_map) {
+        fprintf(fp, ")");
+      }
     }
     break;
   case SPICE_SRAM_MEMORY_BANK: