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Bug fix for non fracturable LUT

This commit is contained in:
AurelienUoU 2019-08-14 09:32:15 -06:00
parent 30c0f2b6b7
commit df873903f8
1 changed files with 18 additions and 18 deletions
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36
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
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@ -656,25 +656,25 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
} }
if (0 < num_mode_sram) { if (0 < num_mode_sram) {
fprintf(fp, ", "); fprintf(fp, ", ");
} if (TRUE == subckt_require_explicit_port_map) {
if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".mode_out( ");
fprintf(fp, ".mode_out( "); }
} dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 0, VERILOG_PORT_CONKT);
0, VERILOG_PORT_CONKT); if (TRUE == subckt_require_explicit_port_map) {
if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")");
fprintf(fp, ")"); }
}
fprintf(fp, ", "); fprintf(fp, ", ");
if (TRUE == subckt_require_explicit_port_map) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_outb( "); fprintf(fp, ".mode_outb( ");
} }
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT); 1, VERILOG_PORT_CONKT);
if (TRUE == subckt_require_explicit_port_map) { if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")"); fprintf(fp, ")");
}
} }
break; break;
case SPICE_SRAM_MEMORY_BANK: case SPICE_SRAM_MEMORY_BANK: